公开(公告)号：US20180033701A1

公开(公告)日：2018-02-01

申请号：US15728445

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/8238 ,  H01L23/535 ,  H01L21/027 ,  G06F17/50 ,  H01L21/768 ,  H01L21/285 ,  H01L27/092 ,  H01L21/8234

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US09818651B2

公开(公告)日：2017-11-14

申请号：US15067953

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/285 ,  H01L21/027 ,  H01L27/092 ,  H01L23/535 ,  G06F17/50

CPC classification number: H01L21/823871 ,  G06F17/5072 ,  H01L21/027 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US09798852B2

公开(公告)日：2017-10-24

申请号：US15040235

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50 ,  H01L21/027

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  H01L21/027

Abstract: Methods for performing design rule checking of a circuit design are provided. The methods include, for instance: providing a circuit design for an integrated circuit layer, in which the circuit design includes a plurality of design lines oriented in a particular direction; and automatically performing a design rule check of the circuit design, which may include forming a verification pattern for the circuit design, the verification pattern comprising a plurality of verification lines and a plurality of verification regions, wherein one or more verification regions are associated with and connected to one verification line of the plurality of verification lines, and checking the verification pattern for any verification line overlapping a verification region. The circuit design may be considered to fail the design rule check if an end of one verification line overlaps any verification region associated with another verification line of the verification pattern.

公开(公告)号：US09536035B2

公开(公告)日：2017-01-03

申请号：US14809698

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: H01L23/52 ,  G06F17/50 ,  H01L23/522 ,  H01L27/02 ,  H01L27/118

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处耦合到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。

公开(公告)号：US09472464B1

公开(公告)日：2016-10-18

申请号：US15060691

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jia Zeng ,  Lei Yuan ,  Youngtag Woo ,  Yan Wang ,  Jongwook Kye

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/3086 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/785

Abstract: Methods for processes to form and use merged spacers in fin generation and the resulting devices are disclosed. Embodiments include providing first and second mandrels separated from each other across adjacent cells on a Si layer; forming first and second dummy-spacers and third and fourth dummy-spacers on opposite sides of the first and second mandrels, respectively; removing, through a block-mask, the first and fourth dummy spacers and a portion of the second and third dummy-spacers; forming first spacers on each exposed side of the mandrels and in between the second and third dummy-spacers, forming a merged spacer; removing the mandrels; removing a section of the merged-spacer; forming second spacers on all exposed sides of the first spacers and the merged-spacer; removing the merged-spacer and the first spacers; removing exposed sections of the Si layer through the second spacers; and removing the second spacers to reveal Si fins.

Abstract translation: 公开了在翅片生成中形成和使用合并间隔物的方法以及所得装置。 实施例包括提供在Si层上相邻的单元彼此分开的第一和第二心轴; 在第一和第二心轴的相对侧分别形成第一和第二虚拟间隔物和第三和第四虚拟间隔物; 通过块掩模去除第一和第四虚拟间隔物和第二和第三虚拟间隔物的一部分; 在心轴的每个暴露侧上并在第二和第三虚拟间隔件之间形成第一间隔件，形成合并间隔件; 去除心轴; 去除合并间隔物的一部分; 在第一间隔件和合并间隔件的所有暴露侧上形成第二间隔件; 去除合并间隔物和第一间隔物; 通过所述第二间隔物去除所述Si层的暴露部分; 并且移除第二间隔件以露出Si散热片。

公开(公告)号：US09324722B1

公开(公告)日：2016-04-26

申请号：US14797757

申请日：2015-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Lei Yuan ,  Jongwook Kye

IPC: H01L21/4763 ,  H01L27/11 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L21/76829 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

Abstract: A method of forming metal routing in an IC device utilizing a cut mask in conjunction with a block mask is disclosed. Embodiments include forming a hard-mask layer on an upper surface of a silicon-oxide layer; forming spaced parallel mandrels on an upper surface of the hard-mask; forming spacers on opposite sides of each mandrel, removing the mandrels, forming alternating mandrel and non-mandrel spaces; forming block-mask portions over the mandrel and non-mandrel spaces; removing exposed sections of the hard-mask exposing sections of the silicon-oxide, removing the block-mask portions; forming a cut-mask with openings shorter than the block-mask portions over the upper surface of the hard-mask where the block-mask portions had been; removing the hard-mask through the cut-mask openings, removing the cut-mask; forming cavities in exposed regions of the silicon-oxide; removing the spacers and any remaining hard-mask; and forming metal lines in the cavities.

Abstract translation: 公开了一种利用切割掩模结合块掩模在IC器件中形成金属布线的方法。 实施例包括在氧化硅层的上表面上形成硬掩模层; 在所述硬掩模的上表面上形成间隔开的平行心轴; 在每个心轴的相对侧上形成间隔物，去除心轴，形成交替的心轴和非心轴空间; 在心轴和非心轴空间上形成阻挡掩模部分; 去除所述氧化硅的所述硬掩模暴露部分的暴露部分，去除所述阻挡掩模部分; 在所述硬掩模的上表面上形成具有比所述阻挡掩模部分更短的开口的切割掩模; 通过切割掩模开口去除硬掩模，去除切割掩模; 在氧化硅的暴露区域中形成空腔; 去除间隔物和任何剩余的硬掩模; 并在空腔中形成金属线。

公开(公告)号：US20150286764A1

公开(公告)日：2015-10-08

申请号：US14245868

申请日：2014-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Li Yang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: At least one method disclosed herein involves creating an overall pattern layout for an integrated circuit that is to be manufactured using a self-aligned double patterning (SADP) process, forming a first metal feature having a first width on a first track of a metal layer using the SADP process, forming a second metal feature having a second width on a second track of the metal layer. The second track is adjacent to the first track. The method also includes forming an electrical connection between the first metal feature and the second metal feature to provide an effectively single metal pattern having a third width that is the sum of the first and second widths, rendering the first and second features decomposable using the SADP process; and decomposing e overall pattern layout with the first and second metal features into a mandrel mask pattern and a block mask pattern.

Abstract translation: 本文公开的至少一种方法涉及为使用自对准双图案（SADP）工艺制造的集成电路的整体图案布局，在金属层的第一轨道上形成具有第一宽度的第一金属特征 使用SADP工艺，在金属层的第二轨道上形成具有第二宽度的第二金属特征。 第二条轨道与第一条轨道相邻。 该方法还包括在第一金属特征和第二金属特征之间形成电连接，以提供具有第三宽度的有效单个金属图案，该第三宽度是第一宽度和第二宽度之和，使得第一和第二特征可以使用SADP分解 处理; 并且将第一和第二金属特征的e整体图案布局分解成心轴掩模图案和块掩模图案。

公开(公告)号：US20150113484A1

公开(公告)日：2015-04-23

申请号：US14578717

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Soo Han Choi ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5068

Abstract: One method disclosed herein involves, among other things, generating a set of mandrel mask rules, block mask rules and a virtual, software-based non-mandrel-metal mask. The method also includes creating a set of virtual non-mandrel mask rules that is a replica of the mandrel mask rules, generating a set of metal routing design rules based upon the mandrel mask rules, the block mask rules and the virtual non-mandrel mask rules, generating the circuit routing layout based upon the metal routing design rules, decomposing the circuit routing layout into a mandrel mask pattern and a block mask pattern, generating a first set of mask data corresponding to the mandrel mask pattern, and generating a second set of mask data corresponding to the block mask pattern.

Abstract translation: 本文公开的一种方法尤其涉及生成一组心轴掩模规则，块掩模规则和基于软件的虚拟金属掩模。 该方法还包括创建一组虚拟非心轴掩模规则，该规则是心轴掩模规则的副本，基于心轴掩模规则，块掩模规则和虚拟非心轴掩模生成一组金属路由设计规则 规则，基于金属路由设计规则生成电路布线布局，将电路路由布局分解为心轴掩模图案和块掩模图案，产生对应于心​​轴掩模图案的第一组掩模数据，以及生成第二组 对应于块掩模图案的掩模数据。

公开(公告)号：US08921225B2

公开(公告)日：2014-12-30

申请号：US13766141

申请日：2013-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry Levinson

IPC: H01L21/308 ,  H01L21/28 ,  H01L23/50

CPC classification number: H01L23/49838 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L23/50 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.

Abstract translation: 公开了一种用于有效的非轨道路由的方法以及所得到的设备。 实施例包括：在基板上提供硬掩模; 在硬掩模上提供多个第一心轴; 在每个所述第一心轴的每一侧上提供第一间隔件; 提供所述基板的多个第一非心轴区域与所述第一心轴分开并且在所述第一间隔件中的两个之间，所述第一心轴，第一非心轴区域和第一间隔件中的每一个具有等于一定距离的宽度; 以及提供具有至少两倍距离的宽度的第二心轴，并且通过第二间隔件与第一非心轴区域之一分离。

公开(公告)号：US20140327153A1

公开(公告)日：2014-11-06

申请号：US13886423

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Mahbub Rashed ,  Irene Yuh-Ling Lin ,  Jongwook Kye

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5221 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improving a standard cell connection for circuit routing. Specifically, provided is an IC device having a plurality of cells, a first metal layer (M1) pin coupled to a contact bar extending from a first cell of the plurality of cells, and a second metal layer (M2) wire coupled to the contact bar, wherein the contact bar extends across at least one power rail. By extending the contact bar into an open area between the plurality of cells to couple the M1 pin and the M2 wire, routing efficiency and chip scaling are improved.

Abstract translation: 本文描述的实施例提供了用于改进电路布线的标准单元连接的方法。 具体地，提供有具有多个单元的IC器件，耦合到从多个单元的第一单元延伸的接触棒的第一金属层（M1）引脚和耦合到该触点的第二金属层（M2）线 杆，其中接触杆延伸穿过至少一个电源轨。 通过将接触杆延伸到多个单电池之间的开放区域中以耦合M1引脚和M2线，提高了布线效率和芯片缩放。