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    Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures
    52.
    发明申请
    Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures 有权
    具有交替内存字符串方向和字符串选择结构的3D阵列的内存架构

    公开(公告)号：US20120182806A1

    公开(公告)日：2012-07-19

    申请号：US13078311

    申请日：2011-04-01

    Applicant: Shih-Hung Chen ,  Hang-Ting Lue

    Inventor： Shih-Hung Chen ,  Hang-Ting Lue

    IPC: G11C16/04

    CPC classification number: H01L27/11578 ,  G11C13/0002 ,  G11C16/0483 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/11573

    Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit lines at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of word lines, which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the stacks and the word lines.

    Abstract translation: 3D存储器件包括多个由绝缘材料隔开的导电材料条带形式的脊形叠层，排列成可通过解码电路耦合到读出放大器的位线。 二极管与字符串的公共源选择端的字符串选择连接到位线。 导电材料条具有在脊形叠层的侧面上的侧表面。 可以耦合到行解码器的多个字线在多个脊形叠层上正交延伸。 存储元件位于堆叠上的半导体条的侧表面和字线之间的交叉点处的界面区域的多层阵列中。

    Multi-Layer Single Crystal 3D Stackable Memory
    53.
    发明申请
    Multi-Layer Single Crystal 3D Stackable Memory 有权
    多层单晶3D可堆叠内存

    公开(公告)号：US20120181654A1

    公开(公告)日：2012-07-19

    申请号：US13223116

    申请日：2011-08-31

    Applicant: Hang-Ting Lue

    Inventor： Hang-Ting Lue

    IPC: H01L21/3105 ,  H01L29/06

    CPC classification number: H01L21/3105 ,  H01L21/8221 ,  H01L27/11578

    Abstract: Technology is described herein for manufacturing a three-dimensional 3D stacked memory structure having multiple layers of single crystal silicon or other semiconductor. The multiple layers of single crystal semiconductor are suitable for implementing multiple levels of high performance memory cells.

    Abstract translation: 本文描述了用于制造具有多层单晶硅或其他半导体的三维3D堆叠存储器结构的技术。 多层单晶半导体适用于实现多级高性能存储单元。

    Multiple Patterning Method
    54.
    发明申请
    Multiple Patterning Method 有权
    多种图案化方法

    公开(公告)号：US20120168841A1

    公开(公告)日：2012-07-05

    申请号：US12981121

    申请日：2010-12-29

    Applicant: Shih Hung Chen ,  Hang-Ting Lue

    Inventor： Shih Hung Chen ,  Hang-Ting Lue

    IPC: H01L29/788 ,  G03F7/20

    CPC classification number: H01L27/11565 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/1157 ,  H01L27/11573

    Abstract: An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions.

    Abstract translation: 集成电路存储器包括一组线，每条线在第一区域中具有平行的X方向线部分，在第二区域具有Y方向线部分。 第二区域偏离第一区域。 X方向线部分的长度比Y方向线部分的长度大得多。 X方向和Y方向线部分具有相应的第一和第二间距，其中第二间距比第一间距大至少3倍。 触点拾取区域在Y方向线部分。 在一些示例中，这些线包括字线或位线。 可以使用多个图案化方法来创建记忆，以产生材料线，然后平行的X方向线部分和平行的Y方向线部分。

    Injection method with Schottky source/drain
    55.
    发明授权
    Injection method with Schottky source/drain 有权
    肖特基源/漏极注入法

    公开(公告)号：US08183617B2

    公开(公告)日：2012-05-22

    申请号：US12430817

    申请日：2009-04-27

    Applicant: Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

    Inventor： Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

    IPC: H01L29/76

    CPC classification number: H01L29/665 ,  G11C16/0408 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

    Abstract: An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.

    Abstract translation: 描述了具有肖特基源和漏极的非易失性存储单元的注入方法。 载流子注入效率由硅化物和硅的界面特性控制。 通过控制栅极和源极/漏极的重叠以及通过控制注入，激活和/或栅极过程来修改肖特基势垒。

    3D Memory Array With Improved SSL and BL Contact Layout
    56.
    发明申请
    3D Memory Array With Improved SSL and BL Contact Layout 有权
    3D存储阵列改进的SSL和BL联系布局

    公开(公告)号：US20120007167A1

    公开(公告)日：2012-01-12

    申请号：US13018110

    申请日：2011-01-31

    Applicant: Chun-Hsiung Hung ,  Hang-Ting Lue ,  Shin-Jang Shen

    Inventor： Chun-Hsiung Hung ,  Hang-Ting Lue ,  Shin-Jang Shen

    IPC: H01L29/792 ,  H01L21/8239

    CPC classification number: H01L27/11578 ,  G11C13/0002 ,  G11C16/0483 ,  G11C17/16 ,  G11C2213/71 ,  H01L21/768 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips. Some embodiments include SSL interconnects on a metal layer parallel to the semiconductor material strips, and further SSL interconnects on a higher metal layer, parallel to the word lines.

    Abstract translation: 3D存储器件包括多个脊，在一些实施例中，以绝缘材料隔开的多条导电材料形式的脊形形状，排列成可通过解码电路耦合到读出放大器的位线。 导电材料条具有堆叠侧面上的侧表面。 布置成可以耦合到行解码器的字线的多个导线在多个堆叠上正交延伸。 导线符合堆叠的表面。 存储器元件位于叠层和导电线上的半导体材料条的侧表面之间的交叉点处的界面区域的多层阵列。 存储器元件是可编程的，如抗熔丝或电荷捕获结构。 在一些实施例中，仅使用用于多层的两个临界掩模来制作3D存储器。 一些实施例包括位于半导体材料条的端部处的阶梯状结构。 一些实施例包括平行于半导体材料带的金属层上的SSL互连以及平行于字线的较高金属层上的另外的SSL互连。

    Floating gate memory device with interpoly charge trapping structure
    58.
    发明授权
    Floating gate memory device with interpoly charge trapping structure 有权
    具有互补电荷捕获结构的浮栅存储器件

    公开(公告)号：US08068370B2

    公开(公告)日：2011-11-29

    申请号：US12409935

    申请日：2009-03-24

    Applicant: Hang-Ting Lue

    Inventor： Hang-Ting Lue

    IPC: G11C16/06 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

    CPC classification number: H01L27/115 ,  G11C16/0408 ,  G11C16/10 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7883 ,  H01L29/792

    Abstract: A charge trapping floating gate is described with asymmetric tunneling barriers. The memory cell includes a source region and a drain region separated by a channel region. A first tunneling barrier structure is disposed above the channel region. A floating gate is disposed above the first tunneling barrier structure covering the channel region. A second tunneling barrier is disposed above the floating gate. A dielectric charge trapping structure disposed above the second tunneling barrier and a blocking dielectric structure is disposed above the charge trapping structure. A top conductive layer disposed above the top dielectric structure acts as a gate. The second tunneling barrier is a more efficient conductor of tunneling current, under bias conditions applied for programming and erasing the memory cell, than the first tunneling barrier structure.

    Abstract translation: 电荷捕获浮动栅极用不对称隧道势垒描述。 存储单元包括由沟道区分开的源区和漏区。 第一隧道势垒结构设置在沟道区域的上方。 浮置栅极设置在覆盖沟道区域的第一隧道势垒结构上方。 第二隧道势垒设置在浮动栅极上方。 设置在第二隧道势垒上方的介电电荷俘获结构和阻挡电介质结构设置在电荷俘获结构之上。 设置在顶部电介质结构上方的顶部导电层用作栅极。 第二隧道势垒是在施加用于编程和擦除存储器单元的偏置条件下比第一隧道势垒结构更有效的隧道电流导体。

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