公开(公告)号：US20100207190A1

公开(公告)日：2010-08-19

申请号：US12705231

申请日：2010-02-12

申请人： Ryota KATSUMATA ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Ryota KATSUMATA ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/0688 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line. At least some of the control gate electrodes are pierced by two of the semiconductor pillars adjacent to each other in the second direction. Two of the semiconductor pillars being connected to each other by the connection member pierce mutually different control gate electrodes.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠体，包括交替层叠有多个电极膜的多个绝缘膜，所述电极膜被分割以形成沿第一方向排列的多个控制栅电极; 多个半导体柱沿层叠体的堆叠方向排列，半导体柱沿着第一方向排列成矩阵构造，第二方向与第一方向相交以刺穿控制栅电极; 以及将所述半导体柱之一的下端部连接到所述半导体柱的另一个的下端部的连接部件，所述一个半导体柱的上端部与源极线连接，上端部 另一个半导体柱被连接到位线。 至少一些控制栅极电极在第二方向上被彼此相邻的两个半导体柱刺穿。 通过连接构件彼此连接的两个半导体柱穿透相互不同的控制栅电极。

公开(公告)号：US20100044776A1

公开(公告)日：2010-02-25

申请号：US12535847

申请日：2009-08-05

申请人： Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body and a memory film is formed on an inner surface of the trench. Subsequently, a silicon body is buried inside the trench, and a charge storage film and the silicon body are divided in the word line direction to form silicon pillars. This simplifies the configuration of memory cells in the bit line direction, and hence can shorten the arrangement pitch of the silicon pillars, decreasing the area per memory cell.

摘要翻译： 通过在与硅衬底的上表面正交的方向上交替堆叠用作控制栅极和电介质膜的电极膜来形成多层体。 在多层体中形成在字线方向上延伸的沟槽，并且在沟槽的内表面上形成记忆膜。 随后，将硅体埋在沟槽内，并且电荷存储膜和硅体在字线方向上分开以形成硅柱。 这简化了位线方向上的存储单元的配置，因此可以缩短硅柱的排列间距，减小每个存储单元的面积。

公开(公告)号：US20090267135A1

公开(公告)日：2009-10-29

申请号：US12408249

申请日：2009-03-20

申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Hideaki Aochi ,  Megumi Ishiduki ,  Yasuyuki Matsuoka

发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Hideaki Aochi ,  Megumi Ishiduki ,  Yasuyuki Matsuoka

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L27/11578 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11582

摘要： A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality of first conductive layers; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and a charge accumulation layer formed between the first conductive layers and the first semiconductor layer. Respective ends of the first conductive layers are formed in a stepwise manner in relation to each other in a first direction. The second layer includes: a plurality of second conductive layers extending in parallel to the substrate and laminated in a direction perpendicular to the substrate, the second conductive layers being formed in the same layer as the plurality of first conductive layers; and a second insulation layer formed on an upper layer of the plurality of second conductive layers. Respective ends of the second conductive layers are formed to align along a straight line extending in a direction substantially perpendicular to the substrate at a predetermined area.

摘要翻译： 非易失性半导体存储装置包括第一层和第二层。 第一层包括：多个第一导电层，其平行于衬底延伸并且在垂直于衬底的方向上层压; 形成在所述多个第一导电层的上层上的第一绝缘层; 形成为穿透所述多个第一导电层的第一半导体层; 以及形成在第一导电层和第一半导体层之间的电荷累积层。 第一导电层的相应端部在第一方向上相对于彼此以逐步的方式形成。 第二层包括：多个第二导电层，其平行于衬底延伸并且在垂直于衬底的方向上层叠，第二导电层形成在与多个第一导电层相同的层中; 以及形成在所述多个第二导电层的上层上的第二绝缘层。 形成第二导电层的相应端，沿着在预定区域上基本上垂直于衬底的方向延伸的直线对齐。

公开(公告)号：US20090230462A1

公开(公告)日：2009-09-17

申请号：US12393509

申请日：2009-02-26

申请人： Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11578 ,  H01L27/11582

摘要： Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction. Respective ends of the plurality of first conductive layers in the first direction are formed in a stepwise manner in relation to each other, entirety of the plurality of the second conductive layers are formed in an area immediately above the top layer of the first conductive layers, and the plurality of first conductive layers and the plurality of second conductive layers are covered with a protection insulation layer that is formed continuously with the plurality of first conductive layers and the second conductive layers.

摘要翻译： 每个存储器串包括：在垂直方向上延伸到衬底的第一柱状半导体层; 多个第一导电层，其形成为夹着具有电荷陷阱层的绝缘层并以二维方式扩展; 第二柱状半导体层，其与所述第一柱状半导体层的顶表面接触并且在垂直方向上延伸到所述衬底; 以及多个第二导电层，其形成为与第二柱状半导体层夹着绝缘层，并且形成为沿与垂直方向正交的第一方向延伸的条纹图案。 多个第一导电层的第一方向的端部相对于彼此分步地形成，多个第二导电层的整体形成在第一导电层的顶层的正上方的区域中， 并且多个第一导电层和多个第二导电层被与多个第一导电层和第二导电层连续形成的保护绝缘层覆盖。

公开(公告)号：US20090224309A1

公开(公告)日：2009-09-10

申请号：US12389977

申请日：2009-02-20

申请人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L21/8221 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A method for manufacturing a nonvolatile semiconductor storage device, including: forming a first conductive layer so that it is sandwiched in an up-down direction by first insulating layers; forming a first hole so that it penetrates the first insulating layers and the first conductive layer; forming a first side wall insulating layer on a side wall facing the first hole; forming a sacrificing layer so that the sacrificing layer infills the first hole; forming a second conductive layer on an upper layer of the sacrificing layer so that the second conductive layer is sandwiched by the second insulating layer in an up-down direction; forming a second hole on a position which matches with the first hole so that the second hole penetrates the second insulating layer and the second conductive layer; forming a second side wall insulating layer on a side wall facing the second hole; removing the sacrificing layer after the formation of the second side wall insulating layer; and forming a semiconductor layer so that the semiconductor layer infills the first hole and the second hole after the removal of the sacrificing layer

摘要翻译： 一种制造非易失性半导体存储装置的方法，包括：形成第一导电层，使其通过第一绝缘层沿上下方向夹持; 形成第一孔，使其穿透第一绝缘层和第一导电层; 在面向所述第一孔的侧壁上形成第一侧壁绝缘层; 形成牺牲层，使牺牲层填充第一孔; 在牺牲层的上层上形成第二导电层，使得第二导电层在上下方向上被第二绝缘层夹持; 在与所述第一孔匹配的位置上形成第二孔，使得所述第二孔穿过所述第二绝缘层和所述第二导电层; 在面向所述第二孔的侧壁上形成第二侧壁绝缘层; 在形成第二侧壁绝缘层之后去除牺牲层; 以及形成半导体层，使得半导体层在去除牺牲层之后填充第一孔和第二孔

公开(公告)号：US20090101969A1

公开(公告)日：2009-04-23

申请号：US12248577

申请日：2008-10-09

申请人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a semiconductor substrate; a first conductive layer provided on a surface of the substrate and serving as one of a source and a drain; a first insulating film provided on the first conductive layer; a gate electrode film provided on the first insulating film; a second insulating film provided on the gate electrode film; a gate opening provided so as to penetrate the second insulating film, the gate electrode film and the first insulating film to expose a part of the first conductive layer; a recess provided in the surface of the first conductive layer just below the gate opening; a gate insulator provided on the side surface of the gate opening and having a projecting shape at a portion between the first insulating film and the recess; a second conductive layer buried in the recess and in a bottom of the gate opening so as to be in contact with the gate insulator, and serving as the one of the source and the drain while being in contact with the first conductive layer; a channel which is buried in the gate opening above the second conductive layer so as to face the gate electrode film with the gate insulator therebetween, and which has a channel layer generated therein, the channel layer allowing majority carriers to flow between the source and the drain in response to a voltage applied to the gate; and a third conductive layer buried in the gate opening above the channel so as to be in contact with the gate insulator to serve as the other one of the source and the drain.

摘要翻译： 一种半导体器件，包括：半导体衬底; 设置在所述基板的表面上并用作源极和漏极之一的第一导电层; 设置在所述第一导电层上的第一绝缘膜; 设置在所述第一绝缘膜上的栅电极膜; 设置在栅电极膜上的第二绝缘膜; 设置为穿透第二绝缘膜的栅极开口，栅极电极膜和第一绝缘膜，以暴露第一导电层的一部分; 设置在所述第一导电层的位于所述栅极开口正下方的表面中的凹部; 栅极绝缘体，其设置在所述栅极开口的侧表面上，并且在所述第一绝缘膜和所述凹部之间的部分处具有突出形状; 第二导电层，其被埋置在所述凹部中并且位于所述栅极开口的底部以与所述栅极绝缘体接触，并且在与所述第一导电层接触的同时用作所述源极和漏极中的一个; 埋入在第二导电层上方的栅极开口中以与门极绝缘体相对的栅极电极膜并且其中产生沟道层的沟道，该沟道层允许多数载流子在源极和源极之间流动 响应于施加到门的电压而漏极; 以及掩埋在沟道上方的栅极开口中的第三导电层，以便与栅极绝缘体接触以用作源极和漏极中的另一个。

公开(公告)号：US20080315291A1

公开(公告)日：2008-12-25

申请号：US12140734

申请日：2008-06-17

申请人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

发明人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/00 ,  H01L21/31

CPC分类号： H01L27/105 ,  H01L21/02161 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31645 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.

摘要翻译： 非易失性半导体存储器件具有多个存储串，每个存储串包括串联连接的多个电可重写存储器单元。 存储器串包括从基板沿垂直方向延伸的柱状半导体部分，与柱状半导体部分相邻形成并构成为积蓄电荷的第一电荷存储层，与第一电荷存储层相邻形成的第一块绝缘体， 第一导体与第一块绝缘体相邻形成。

公开(公告)号：US20080180994A1

公开(公告)日：2008-07-31

申请号：US11955900

申请日：2007-12-13

申请人： Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Masaru Kito ,  Hideaki Aochi ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

发明人： Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Masaru Kito ,  Hideaki Aochi ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

IPC分类号： G11C11/34 ,  H01L29/76 ,  G11C8/00

CPC分类号： H01L27/115 ,  G11C7/18 ,  G11C8/08 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select transistors, a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a charge-accumulating function, second dummy transistors formed above said memory cell transistors, and second select transistors formed above said second dummy transistors; wherein a first potential is provided to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors and a second potential is provided to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time of write operation to write data to said memory cell transistors.

摘要翻译： 半导体存储器件具有半导体衬底，形成在所述半导体衬底的表面上的第一选择晶体管，形成在所述第一选择晶体管上方的第一虚拟晶体管，形成在所述第一虚拟晶体管上方的多个存储单元晶体管， 垂直于所述半导体衬底的表面，每个所述存储单元晶体管包括具有电荷累积功能的绝缘层，形成在所述存储单元晶体管上方的第二虚拟晶体管以及形成在所述第二虚设晶体管上方的第二选择晶体管; 其中第一电位被提供给所述第一选择晶体管的栅电极和所述第一虚拟晶体管的栅电极，并且第二电位被提供给所述第二选择晶体管的栅极和所述第二虚设晶体管的栅电极 写入操作的时间将数据写入到所述存储单元晶体管。

公开(公告)号：US08728919B2

公开(公告)日：2014-05-20

申请号：US13723601

申请日：2012-12-21

申请人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Megumi Ishiduki ,  Yosuke Komori ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi

发明人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Megumi Ishiduki ,  Yosuke Komori ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi

IPC分类号： H01L21/20

CPC分类号： H01L29/7926 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.

摘要翻译： 非挥发性半导体存储装置包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元。 每个存储器串包括：第一半导体层，包括相对于衬底在垂直方向上延伸的柱状部分; 多个第一导电层，经由绝缘层形成为围绕柱状部分的侧表面，并以垂直方向上的一定间距形成，第一导电层用作存储器单元的浮动栅极; 以及形成为经由绝缘层包围第一导电层并且用作存储单元的控制电极的多个第二导电层。 每个第一导电层在垂直方向上具有比每个第二导电层的垂直方向上的长度短的长度。

公开(公告)号：US08436414B2

公开(公告)日：2013-05-07

申请号：US12706127

申请日：2010-02-16

申请人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Junya Matsunami ,  Ryouhei Kirisawa

发明人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Junya Matsunami ,  Ryouhei Kirisawa

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 设置在所述半导体基板上的层叠体，具有交替堆叠的电极膜和绝缘膜的层叠体， 第一和第二半导体柱; 以及第一和第二电荷存储层。 第一半导体柱和第二半导体柱设置在层叠体的层叠方向上贯穿层叠体的贯通孔内。 当沿垂直于堆叠方向的方向切割时，通孔具有扁圆形的横截面。 第一和第二半导体柱在第一扁圆的长轴方向上彼此面对。 第一和第二半导体柱沿层叠方向延伸。 第一和第二电荷存储层分别设置在电极膜和第一和第二半导体柱之间。