公开(公告)号：US08890626B2

公开(公告)日：2014-11-18

申请号：US13586033

申请日：2012-08-15

申请人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Iuan Liu

发明人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Iuan Liu

IPC分类号： H03K3/03

CPC分类号： H03K3/0322 ,  H03K3/0315 ,  H03L7/083 ,  H03L7/087 ,  H03L7/089 ,  H03L7/099

摘要： One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

摘要翻译： 本文提供了一种用于无分频锁相环（PLL）和相关相位检测器（PD）的技术和系统。 在一些实施例中，接收脉冲相位检测器（pulsePD）信号，压控振荡器正差分（VCOP）信号和压控振荡器负差分（VCON）信号。 基于pulsePD信号，VCOP信号和VCON信号产生用于第一电荷泵（CP）的上升信号和下降信号以及用于第二CP的上升信号和下降信号。 例如，生成CP信号以分别控制第一CP和第二CP。 在一些实施例中，产生CP信号，使得CP有助于调整相对于pulsePD信号的VCON和VCOP信号的零交叉相位。 以这种方式，提供无分频PLL，从而减轻PLL功耗。

公开(公告)号：US08847321B2

公开(公告)日：2014-09-30

申请号：US12766972

申请日：2010-04-26

申请人： Fu-Lung Hsueh ,  Chih-Ping Chao ,  Chewn-Pu Jou ,  Yung-Chow Peng ,  Harry-Hak-Lay Chuang ,  Kuo-Tung Sung

发明人： Fu-Lung Hsueh ,  Chih-Ping Chao ,  Chewn-Pu Jou ,  Yung-Chow Peng ,  Harry-Hak-Lay Chuang ,  Kuo-Tung Sung

IPC分类号： H01L29/78 ,  G06F17/50 ,  H01L27/088

CPC分类号： G06F17/5068 ,  G06F17/50 ,  G06F17/5009 ,  H01L27/088 ,  H01L27/0922

摘要： A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.

摘要翻译： MOS器件包括具有第一和第二触点的有源区。 第一和第二栅极设置在第一和第二触点之间。 第一门被设置成与第一接触相邻并且具有第三接触。 第二栅极被设置成与第二触点相邻并且具有耦合到第三触点的第四触点。 由有源区和第一栅极限定的晶体管具有第一阈值电压，并且由有源区和第二栅极限定的晶体管具有第二阈值电压。

公开(公告)号：US08768994B2

公开(公告)日：2014-07-01

申请号：US12910232

申请日：2010-10-22

申请人： Feng Wei Kuo ,  Mei-Show Chen ,  Chewn-Pu Jou ,  Ying-Ta Lu ,  Jia-Liang Chen

发明人： Feng Wei Kuo ,  Mei-Show Chen ,  Chewn-Pu Jou ,  Ying-Ta Lu ,  Jia-Liang Chen

IPC分类号： G06F17/10 ,  H04N5/50 ,  H04L27/06 ,  H04B1/18

CPC分类号： H03H21/0067 ,  H03D3/007 ,  H03H2021/0081 ,  H03H2210/04 ,  H03J2200/08 ,  H03L7/07 ,  H03L7/0816 ,  H03L7/087 ,  H03L7/193 ,  H03L7/1976 ,  H04B1/30

摘要： A filter auto-calibration system includes a multi-clock module. The multi-clock module includes a multi-clock generator that is configured to generate a clock signal with a variable frequency based on a channel setting. There is at least one filter to be calibrated. An auto-calibration control module is configured to control calibration of the at least one filter based on the channel setting. The multi-clock module is configured to supply the variable frequency clock signal to the at least one filter and to the auto-calibration control module, and the at least one filter is coupled to the auto-calibration control module.

摘要翻译： 滤波器自动校准系统包括多时钟模块。 多时钟模块包括多时钟发生器，其被配置为基于通道设置产生具有可变频率的时钟信号。 至少有一个要校准的过滤器。 自动校准控制模块被配置为基于通道设置来控制至少一个滤波器的校准。 多时钟模块被配置为将可变频率时钟信号提供给至少一个滤波器和自动校准控制模块，并且至少一个滤波器耦合到自动校准控制模块。

公开(公告)号：US08729968B2

公开(公告)日：2014-05-20

申请号：US13103571

申请日：2011-05-09

申请人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H03L5/00

CPC分类号： G01R31/2824

摘要： A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

摘要翻译： 用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。 射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。 此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。 另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

公开(公告)号：US08664729B2

公开(公告)日：2014-03-04

申请号：US13325922

申请日：2011-12-14

申请人： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

发明人： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

IPC分类号： H01L27/088

CPC分类号： H01L29/66795 ,  H01L29/42372 ,  H01L29/785

摘要： Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed.

摘要翻译： 降低栅极电阻finFET的方法和装置。 公开了一种金属栅极晶体管结构，其包括形成在半导体衬底上的多个半导体鳍片，所述鳍片平行布置并间隔开; 一个含金属的栅电极，形成在半导体衬底之上，并且覆盖每个半导体鳍片的沟道栅极区域，并且在半导体鳍片之间的半导体衬底上延伸; 覆盖所述栅电极和所述半导体衬底的层间电介质层; 以及多个触点，其布置在所述层间电介质层中并且延伸穿过所述层间电介质层到所述栅电极; 形成在所述层间电介质层上并且由所述多个触点耦合到所述栅电极的低电阻金属带; 其中所述多个触点与所述半导体鳍片的沟道栅极区域间隔开。 公开了形成栅极finFET的方法。

公开(公告)号：US08626469B2

公开(公告)日：2014-01-07

申请号：US12907586

申请日：2010-10-19

申请人： Dipankar Nag ,  Mei-Show Chen ,  Chewn-Pu Jou

发明人： Dipankar Nag ,  Mei-Show Chen ,  Chewn-Pu Jou

IPC分类号： H03B1/00 ,  H03K5/00

CPC分类号： H03H11/1291 ,  H03H2011/0494 ,  H03H2210/025 ,  H03H2210/04 ,  H03J2200/08

摘要： A method of calibrating a filter includes applying an input signal into the filter to generate an output signal, measuring a phase difference between the input signal and the output signal; determining a leading/lagging status of the phase difference; calculating a capacitor code (CAP_CODE) using the leading/lagging status; and calibrating the capacitor using the CAP_CODE.

摘要翻译： 校准滤波器的方法包括将输入信号施加到滤波器中以产生输出信号，测量输入信号和输出信号之间的相位差; 确定相位差的前导/滞后状态; 使用前导/滞后状态计算电容代码（CAP_CODE）; 并使用CAP_CODE校准电容器。

公开(公告)号：US08547151B2

公开(公告)日：2013-10-01

申请号：US13407394

申请日：2012-02-28

申请人： Feng Wei Kuo ,  Shyh-An Chi ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Chewn-Pu Jou

发明人： Feng Wei Kuo ,  Shyh-An Chi ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Chewn-Pu Jou

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/06 ,  H03L7/093 ,  H03L7/099

摘要： A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits.

摘要翻译： 集成电路的管芯堆叠包括多个管芯。 芯片堆叠中的每个裸片包括锁相环（PLL）。 每个模具中的PLL共享一个环路滤波器和其他相应的电路。

公开(公告)号：US20130154011A1

公开(公告)日：2013-06-20

申请号：US13325922

申请日：2011-12-14

申请人： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

发明人： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/42372 ,  H01L29/785

摘要： Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed.

摘要翻译： 降低栅极电阻finFET的方法和装置。 公开了一种金属栅极晶体管结构，其包括形成在半导体衬底上的多个半导体鳍片，所述鳍片平行布置并间隔开; 一个含金属的栅电极，形成在半导体衬底之上，并且覆盖每个半导体鳍片的沟道栅极区域，并且在半导体鳍片之间的半导体衬底上延伸; 覆盖所述栅电极和所述半导体衬底的层间电介质层; 以及多个触点，其布置在所述层间电介质层中并且延伸穿过所述层间电介质层到所述栅电极; 形成在所述层间电介质层上并且由所述多个触点耦合到所述栅电极的低电阻金属带; 其中所述多个触点与所述半导体鳍片的沟道栅极区域间隔开。 公开了形成栅极finFET的方法。

公开(公告)号：US08334571B2

公开(公告)日：2012-12-18

申请号：US12731562

申请日：2010-03-25

申请人： Ming-Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： Ming-Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H01L23/60 ,  H01L23/64 ,  H01L29/08

CPC分类号： H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.

摘要翻译： ESD保护装置包括设置在形成第一二极管的第二半导体类型的衬底中的第一半导体类型的第一阱。 第二半导体类型的第二阱形成在衬底中以与第一阱形成第二二极管。 第一半导体类型的第一多个掺杂区域形成在第一阱的上表面中。 第二半导体类型的第二多个掺杂区域形成在第一阱的上表面中，其与第一阱形成第三二极管。 多个STI区域形成在第一阱的上表面中。 每个STI区域设置在第一和第二半导体类型的掺杂区域之间。 当在第一或第二多个掺杂区域中的一个处接收ESD电压尖峰时，第三二极管提供电流旁路。

公开(公告)号：US20120074515A1

公开(公告)日：2012-03-29

申请号：US12889650

申请日：2010-09-24

申请人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Sally Liu

发明人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Sally Liu

IPC分类号： H01L29/08

CPC分类号： H01L23/66 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/585 ,  H01L29/0619 ,  H01L2223/6616 ,  H01L2223/6666 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate.

摘要翻译： 一种装置包括具有前表面和后表面的基板; 在基板的前表面上的集成电路器件; 以及在所述基板的背面上的金属板，其中所述金属板与所述集成电路器件的整体重叠。 保护环延伸到基板中并且环绕集成电路装置。 保护环由导电材料形成。 贯穿基板通孔（TSV）穿透基板并与金属板电耦合。