公开(公告)号：US11164942B1

公开(公告)日：2021-11-02

申请号：US16885040

申请日：2020-05-27

Applicant: IMEC VZW

Inventor： Pieter Weckx ,  Julien Ryckaert ,  Eugenio Dentoni Litta

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/311 ,  H01L29/66

Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second nanosheet transistor structure, each comprising a source, a drain, and a channel extending between the source and the drain in a first direction, and a gate extending across the channel, wherein the first and second nanosheet transistor structures are spaced apart in a second direction, transverse to the first direction, by an insulating wall extending in the first direction.

公开(公告)号：US20210193821A1

公开(公告)日：2021-06-24

申请号：US17112844

申请日：2020-12-04

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L23/528 ,  H01L21/02 ,  H01L21/8238

Abstract: In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure. Further, the method can comprise etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact contacting the first source/drain portion of the first transistor structure, and a second contact contacting the first source/drain portion of the second transistor structure.

公开(公告)号：US20190386011A1

公开(公告)日：2019-12-19

申请号：US16441725

申请日：2019-06-14

Applicant: IMEC vzw

Inventor： Pieter Weckx ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H01L27/11 ,  G11C5/02 ,  G11C5/06 ,  G11C11/412 ,  H01L21/822 ,  H01L21/8238

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a semiconductor device comprising stacked complementary transistor pairs. In one aspect, a semiconductor device comprises first and second sets of transistors comprising a pass transistor and a stacked complementary transistor pair of a lower transistor and an upper transistor, wherein first transistor comprises a semiconductor channel extending along a horizontal first fin track, and each second transistor comprises a semiconductor channel extending along a second fin track parallel to the first fin track, and wherein the semiconductor channels of the pass transistors and of the lower transistors are arranged at a first level and the semiconductor channels of said upper transistors are arranged at a second level, a first tall gate electrode forming a common gate for the first complementary transistor pair and arranged along a horizontal first gate track, and a first short gate electrode forming a gate for the first pass transistor and arranged along a second gate track, a second tall gate electrode forming a common gate for the second complementary transistor pair and arranged along the second gate track, a second short gate electrode forming a gate for the second pass transistor and arranged along the first gate track, first and second contact arrangements forming a common drain contact for the transistors of the first set and the second set, respectively, and first and second cross-couple contacts extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, and the second tall gate electrode and the first contact arrangement, respectively.

公开(公告)号：US20190303525A9

公开(公告)日：2019-10-03

申请号：US15791210

申请日：2017-10-23

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Syed Muhammad Yasser Sherazi ,  Guillaume Bouche ,  Julien Ryckaert

IPC: G06F17/50 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L21/84 ,  H01L27/02 ,  H01L27/11 ,  H01L27/12

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method. In one aspect, a method of defining routing tracks in a target layer over a standard cell semiconductor device includes forming mandrels and forming a first set and a second set of spacers for defining the routing tracks. The standard cell semiconductor device includes a device layer and the routing tracks for contacting a device layer. The routing tracks include at least two pairs of off-center routing tracks, a central routing track arranged between the pairs of off-center routing tracks, and at least two edge tracks arranged on opposing sides of the at least two pairs of off-center routing tracks. A minimum distance between an off-center routing track and the central routing track next to the off-center routing track is smaller than a minimum distance between adjacent off-center routing tracks.

公开(公告)号：US20180342524A1

公开(公告)日：2018-11-29

申请号：US15980604

申请日：2018-05-15

Applicant: IMEC VZW

Inventor： Julien Ryckaert ,  Naoto Horiguchi ,  Dan Mocuta ,  Trong Huynh Bao

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/15 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642 ,  H01L2029/7858

Abstract: The disclosed technology generally relates semiconductor devices and more particularly to a vertical transistor device, and a method of fabricating the same. In one aspect, the method includes providing, on a substrate, a fin formed of a stack of a first layer, a second layer and a third layer, wherein the second layer is positioned above the first layer and the third layer is positioned above the second layer. The method additionally includes forming a dielectric on the sidewalls of the first and third layers of the fin selectively against a sidewall of the second layer, and the method additionally includes forming a gate contacting layer for contacting a sidewall of the second layer. The first and third layers define a source region and a drain region, respectively, of the vertical transistor device. The second layer defines a channel region of the vertical transistor device. The dielectric on the sidewalls of the first and third layers electrically isolates the source and drain regions from the gate contacting layer.

公开(公告)号：US20180145030A1

公开(公告)日：2018-05-24

申请号：US15810488

申请日：2017-11-13

Applicant: IMEC VZW

Inventor： Eric Beyne ,  Julien Ryckaert

IPC: H01L23/528 ,  H01L27/092 ,  H01L27/12 ,  H01L23/522 ,  H01L21/762 ,  H01L21/84 ,  H01L21/8238

Abstract: An integrated circuit (IC) chip having power and ground rails incorporated in the front end of line (FEOL) is disclosed. In one aspect, these power and ground rails are at the same level as the active devices and are therefore buried deep in the IC, as seen from the front of the chip. The connection from the buried interconnects to the source and drain areas is established by local interconnects. These local interconnects are not part of the back end of line, but they are for the most part embedded in a pre-metal dielectric layer onto which the BEOL is produced. In a further aspect, a power delivery network (PDN) of the IC is located in its entirety on the backside of the chip. The PDN is connected to the buried interconnects through suitable connections, for example metal-filled through-semiconductor vias or through silicon vias.

公开(公告)号：US20170358586A1

公开(公告)日：2017-12-14

申请号：US15349904

申请日：2016-11-11

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Anabela Veloso ,  Julien Ryckaert

IPC: H01L27/11 ,  H01L29/423 ,  H01L23/528 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L27/0688 ,  H01L27/1104 ,  H01L29/0676 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/78642 ,  H01L29/7869

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.

公开(公告)号：US20170278752A1

公开(公告)日：2017-09-28

申请号：US15459991

申请日：2017-03-15

Applicant: IMEC VZW

Inventor： Julien Ryckaert ,  Juergen Boemmels

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L27/088 ,  H01L21/3213 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/66545

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to electrical contacts to a transistor device, and a method of making such electrical contacts. In one aspect, a method of forming one or more self-aligned gate contacts in a semiconductor device includes providing a substrate having formed thereon at least one gate stack, where the gate stack includes a gate dielectric and a gate electrode formed over an active region in or on the substrate, and where the substrate further has formed thereon a spacer material coating lateral sides of the at least one gate stack. The method additionally includes selectively recessing the gate electrode of the at least one gate stack against the spacer material, thereby creating a first set of recess cavities. The method additionally includes filling the first set of recess cavities with a dielectric material gate cap. The method additionally includes etching at least one via above the at least one gate stack and through the dielectric material gate cap, where etching the at least one via comprises selectively etching against the spacer material, thereby exposing the gate electrode. The method further includes forming, in the at least one via, a gate contact electrically connecting the gate electrode.