公开(公告)号：US20180006115A1

公开(公告)日：2018-01-04

申请号：US15635300

申请日：2017-06-28

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Christian Philipp Sandow ,  Franz-Josef Niedernostheide

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/739 ,  H01L29/10 ,  H01L29/423 ,  H01L29/417 ,  H01L29/36

CPC classification number: H01L29/0696 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/7395 ,  H01L29/7802

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, first and second cells electrically connected to the first load terminal structure and to a drift region, the drift region having a first conductivity type; a first mesa in the first cell and including: a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region; a second mesa in the second cell and including: a port region of the opposite conductivity type and electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure. The insulation structure houses a control electrode structure, and a guidance electrode arranged between the mesas.

公开(公告)号：US20170250271A1

公开(公告)日：2017-08-31

申请号：US15594269

申请日：2017-05-12

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7397 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/7813

Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

公开(公告)号：US09741795B2

公开(公告)日：2017-08-22

申请号：US14854396

申请日：2015-09-15

Applicant: Infineon Technologies AG

Inventor： Christian Philipp Sandow ,  Hans-Joachim Schulze ,  Johannes Georg Laven ,  Franz-Josef Niedernostheide ,  Frank Pfirsch ,  Hans-Peter Felsl

IPC: H01L29/10 ,  H01L29/739 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/1095 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397

Abstract: An IGBT includes at least one first type transistor cell, including a base region, first and second emitter regions, and a body region arranged between the first emitter region and base region. The base region is arranged between the body region and second emitter region. A gate electrode adjacent the body region is dielectrically insulated from the body region by a gate dielectric. A base electrode adjacent the base region is dielectrically insulated from the base region by a base electrode dielectric. The base region has a first base region section adjoining the base electrode dielectric and a second base region section arranged between the second emitter region and the first base region section. A ratio between the doping concentration of the first base region section and the doping concentration of the second base region section is at least 10. The base electrode dielectric is thicker than the gate dielectric.

公开(公告)号：US20150349116A1

公开(公告)日：2015-12-03

申请号：US14824388

申请日：2015-08-12

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/7813

Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

Abstract translation: 具有第一主表面和晶体管单元的半导体衬底包括漂移区，漂移区和第一主表面之间的体区，在延伸到漂移区的第一主表面处的有源沟槽，在侧壁处的栅极绝缘层 所述有源沟槽的底侧，所述有源沟槽中的栅极导电层，所述主体区域中的源极区域，并且与所述有源沟槽相邻，所述第一主表面延伸到所述漂移区域中的主体沟槽，所述主体沟槽 邻近身体区域和漂移区域，在体沟槽的侧壁和底侧具有绝缘层，绝缘层相对于在身体的中心处垂直于第一主表面延伸的轴线是不对称的 沟槽，以及导体层。

公开(公告)号：US11843368B2

公开(公告)日：2023-12-12

申请号：US18060639

申请日：2022-12-01

Applicant: Infineon Technologies AG

Inventor： Zheming Li ,  Mark-Matthias Bakran ,  Daniel Domes ,  Robert Maier ,  Franz-Josef Niedernostheide

IPC: H03K17/04 ,  H03K17/042 ,  H03K5/24

CPC classification number: H03K17/04206 ,  H03K5/24 ,  H03K17/042 ,  H03K17/0406

Abstract: A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

公开(公告)号：US11031929B1

公开(公告)日：2021-06-08

申请号：US16943318

申请日：2020-07-30

Applicant: Infineon Technologies AG

Inventor： Robert Maier ,  Mark-Matthias Bakran ,  Daniel Domes ,  Zheming Li ,  Franz-Josef Niedernostheide

IPC: H03K17/042 ,  H03K17/687 ,  H03K17/95

Abstract: A method of driving a transistor includes generating an off-current during a plurality of turn-off switching events to control a gate voltage at a gate terminal of the transistor, wherein generating the off-current includes sinking a first portion of the off-current from the gate terminal to discharge a first portion of the gate voltage, and sinking, during a boost interval, a second portion of the off-current from the gate terminal to discharge a second portion of the gate voltage; measuring a transistor parameter indicative of an oscillation of a drain-source voltage of the transistor for a first turn-off switching event during which the transistor is transitioned off; activating the first portion of the off-current for a second turn-off switching event; and activating the second portion of the off-current for the second turn-off switching event, including regulating a length of the boost interval based on the measured transistor parameter.

公开(公告)号：US10680089B2

公开(公告)日：2020-06-09

申请号：US16456895

申请日：2019-06-28

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L27/115 ,  H01L27/105 ,  H01L27/11521

Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive gate trench of the device for the same gate potential condition.

公开(公告)号：US10672767B2

公开(公告)日：2020-06-02

申请号：US16507152

申请日：2019-07-10

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/423 ,  H03K17/687 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/49

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, and first and second cells each configured for controlling a load current and electrically connected to the first load terminal structure and to a drift region. A first mesa in the first cell includes a port region electrically connected to the first load terminal structure, and a first channel region coupled to the drift region. A second mesa included in the second cell includes a port region electrically connected to the first load terminal structure, and a second channel region coupled to the drift region. The mesas are spatially confined in a direction perpendicular to a direction of the load current by an insulation structure, and have a total extension of less than 100 nm in that direction. The first channel region includes an inversion channel. The second channel region includes an accumulation channel.

公开(公告)号：US20190371794A1

公开(公告)日：2019-12-05

申请号：US16507152

申请日：2019-07-10

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/739 ,  H03K17/687 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, and first and second cells each configured for controlling a load current and electrically connected to the first load terminal structure and to a drift region. A first mesa in the first cell includes a port region electrically connected to the first load terminal structure, and a first channel region coupled to the drift region. A second mesa included in the second cell includes a port region electrically connected to the first load terminal structure, and a second channel region coupled to the drift region. The mesas are spatially confined in a direction perpendicular to a direction of the load current by an insulation structure, and have a total extension of less than 100 nm in that direction. The first channel region includes an inversion channel. The second channel region includes an accumulation channel.

公开(公告)号：US10453918B2

公开(公告)日：2019-10-22

申请号：US16189858

申请日：2018-11-13

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/36 ,  H01L29/417

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, first and second cells electrically connected to the first load terminal structure and to a drift region, the drift region having a first conductivity type; a first mesa in the first cell and including: a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region; a second mesa in the second cell and including: a port region of the opposite conductivity type and electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure. The insulation structure houses a control electrode structure, and a guidance electrode arranged between the mesas.