公开(公告)号：US10903372B2

公开(公告)日：2021-01-26

申请号：US15770009

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC: H01L29/8605 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: Metal-oxide-polysilicon tunable resistors and methods of fabricating metal-oxide-polysilicon tunable resistors are described. In an example, a tunable resistor includes a polysilicon resistor structure disposed above a substrate. A gate oxide layer is disposed on the polysilicon resistor structure. A metal gate layer is disposed on the gate oxide layer.

公开(公告)号：US10854607B2

公开(公告)日：2020-12-01

申请号：US16853545

申请日：2020-04-20

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L Dias ,  Chanaka D Munasinghe

IPC: H01L27/092 ,  H01L21/82 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L29/08

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.

公开(公告)号：US10784378B2

公开(公告)日：2020-09-22

申请号：US16318108

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Roman W. Olac-Vaw ,  Joodong Park ,  Chen-Guan Lee ,  Chia-Hong Jan ,  Everett S. Cassidy-Comfort

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/66

Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.

公开(公告)号：US10763209B2

公开(公告)日：2020-09-01

申请号：US15327338

申请日：2014-08-19

Applicant: INTEL CORPORATION

Inventor： Roman Olac-Vaw ,  Walid Hafez ,  Chia-Hong Jan ,  Hsu-Yu Chang ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC: H01L29/78 ,  H01L23/525 ,  H01L29/423 ,  H01L29/66 ,  G11C17/16 ,  H01L21/768 ,  H01L27/112

Abstract: A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.

公开(公告)号：US20200251471A1

公开(公告)日：2020-08-06

申请号：US16853545

申请日：2020-04-20

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L. Dias ,  Chanaka D. Munasinghe

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.

公开(公告)号：US20190287973A1

公开(公告)日：2019-09-19

申请号：US16430203

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L. Dias ,  Chanaka D. Munasinghe

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L21/225 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.

公开(公告)号：US20190123164A1

公开(公告)日：2019-04-25

申请号：US16230454

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Chen-Guan Lee ,  Joodong Park ,  En-Shao Liu ,  Everett S. Cassidy-Comfort ,  Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764

Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

公开(公告)号：US09929090B2

公开(公告)日：2018-03-27

申请号：US15117621

申请日：2014-03-24

Applicant: INTEL CORPORATION

Inventor： Ting Chang ,  Chia-Hong Jan ,  Walid M. Hafez

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/62 ,  G11C17/14 ,  G11C17/16 ,  H01L27/112 ,  H01L27/102

CPC classification number: H01L23/5252 ,  G11C11/005 ,  G11C17/143 ,  G11C17/16 ,  G11C17/165 ,  H01L23/62 ,  H01L27/1021 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1 T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.

公开(公告)号：US09911815B2

公开(公告)日：2018-03-06

申请号：US15126812

申请日：2014-06-18

Applicant: INTEL CORPORATION

Inventor： Nidhi Nidhi ,  Chia-Hong Jan ,  Walid M. Hafez

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L23/66

CPC classification number: H01L29/402 ,  H01L21/26513 ,  H01L23/66 ,  H01L29/1083 ,  H01L29/401 ,  H01L29/404 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: Planar and non-planar field effect transistors with extended-drain structures, and techniques to fabricate such structures. In an embodiment, a field plate electrode is disposed over an extended-drain, with a field plate dielectric there between. The field plate is disposed farther from the transistor drain than the transistor gate. In a further embodiment, an extended-drain transistor has source and drain contact metal at approximately twice a pitch, of the field plate and the source and/or drain contact metal. In a further embodiment, an isolation dielectric distinct from the gate dielectric is disposed between the extended-drain and the field plate. In a further embodiment, the field plate may be directly coupled to one or more of the transistor gate electrode or a dummy gate electrode without requiring upper level interconnection. In an embodiment, a deep well implant may be disposed between a lightly-doped extended-drain and a substrate to reduce drain-body junction capacitance and improve transistor performance.

公开(公告)号：US09806095B2

公开(公告)日：2017-10-31

申请号：US14975645

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.