公开(公告)号：US20210314245A1

公开(公告)日：2021-10-07

申请号：US17235135

申请日：2021-04-20

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Susanne M. BALLE ,  Rahul KHANNA ,  Sujoy SEN ,  Karthik KUMAR

IPC: H04L12/26 ,  G06F16/901 ,  H04B10/25 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/18 ,  G06F1/20 ,  G06F3/06 ,  G06F8/65 ,  G06F9/30 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G08C17/02 ,  G11C5/02 ,  G11C7/10 ,  G11C11/56 ,  G11C14/00 ,  H03M7/30 ,  H03M7/40 ,  H04L12/24 ,  H04L12/931 ,  H04L12/947 ,  H04L29/08 ,  H04L29/06 ,  H04Q11/00 ,  H05K7/14 ,  G06F15/16

Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.

公开(公告)号：US20210107151A1

公开(公告)日：2021-04-15

申请号：US17129982

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Rita H. WOUHAYBI ,  Anahit TARKHANYAN ,  Vinayak HONKOTE ,  Rajesh POORNACHANDRAN ,  Francesc GUIM BERNAT

IPC: B25J9/16

Abstract: A device including a processor configured to detect an environment of an automated machine, wherein the environment comprises one or more further automated machines; determine an action taken by the one or more further automated machines; determine an action expected of the one or more further automated machines; compares the taken action with the expected action; determine an accuracy score associated with the one or more further automated machines based on the comparison.

公开(公告)号：US20210048958A1

公开(公告)日：2021-02-18

申请号：US16537649

申请日：2019-08-12

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT

IPC: G06F3/06 ,  G06F13/16

Abstract: Examples relate to a processor apparatus, device, method and computer program, to a memory performance controller apparatus, device, method and computer program and to a memory controller apparatus, device, method and computer program. The processor apparatus comprises interface circuitry for communicating with other components of the computer system. The processing circuitry is configured to provide an interface for controlling a memory performance requirement of a data structure stored within a memory of the computer system. The memory performance requirement is a percentile-based memory performance requirement comprising at least a first memory performance requirement valid for a first portion of access operations and a second memory performance requirement valid for a second portion of access operations. The processing circuitry is configured to control a memory system of the computer system to provide the memory performance indicated by the memory performance requirement in response to an instruction obtained via the interface for controlling the memory performance requirement of the data structure.

公开(公告)号：US20190317802A1

公开(公告)日：2019-10-17

申请号：US16448860

申请日：2019-06-21

Applicant: Intel Corporation

Inventor： Alexander BACHMUTSKY ,  Andrew J. HERDRICH ,  Patrick CONNOR ,  Raghu KONDAPALLI ,  Francesc GUIM BERNAT ,  Scott P. DUBAL ,  James R. HEARN ,  Kapil SOOD ,  Niall D. MCDONNELL ,  Matthew J. ADILETTA

IPC: G06F9/48 ,  G06F9/50

Abstract: Examples are described herein that can be used to offload a sequence of work events to one or more accelerators to a work scheduler. An application can issue a universal work descriptor to a work scheduler. The universal work descriptor can specify a policy for scheduling and execution of one or more work events. The universal work descriptor can refer to one or more work events for execution. The work scheduler can, in some cases, perform translation of the universal work descriptor or a work event descriptor for compatibility and execution by an accelerator. The application can receive notice of completion of the sequence of work from the work scheduler or an accelerator.

公开(公告)号：US20190250916A1

公开(公告)日：2019-08-15

申请号：US16336884

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Patrick LU ,  Karthik KUMAR ,  Thomas WILLHALM ,  Francesc GUIM BERNAT ,  Martin P. DIMITROV

IPC: G06F9/30 ,  G06F12/0862 ,  G06F12/0811

CPC classification number: G06F9/30047 ,  G06F9/30043 ,  G06F9/383 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/6028

Abstract: An apparatus is described. The apparatus includes main memory control logic circuitry comprising prefetch intelligence logic circuitry. The prefetch intelligence circuitry to determine, from a read result of a load instruction, an address for a dependent load that is dependent on the read result and direct a read request for the dependent load to a main memory to fetch the dependent load's data.

公开(公告)号：US20190227978A1

公开(公告)日：2019-07-25

申请号：US16373339

申请日：2019-04-02

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Mustafa HAJEER

IPC: G06F15/173 ,  H04L29/08 ,  G06F15/167 ,  H04L29/06

Abstract: An apparatus is described. The apparatus includes logic circuitry embedded in at least one of a memory controller, network interface and peripheral control hub to process a function as a service (FaaS) function call embedded in a request. The request is formatted according to a protocol. The protocol allows a remote computing system to access a memory that is coupled to the memory controller without invoking processing cores of a local computing system that the memory controller is a component of.

公开(公告)号：US20190227737A1

公开(公告)日：2019-07-25

申请号：US16221743

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Ginger GILSDORF ,  Karthik KUMAR ,  Thomas WILLHALM ,  Mark SCHMISSEUR ,  Francesc GUIM BERNAT

IPC: G06F3/06

Abstract: Examples relate to a method for a memory module, a method for a memory controller, a method for a processor, to a memory module controller device or apparatus, to a memory controller device or apparatus, to a processor device or apparatus, a memory module, a memory controller, a processor, a computer system and a computer program. The method for the memory module comprises obtaining one or more memory write instructions of a group memory write instruction. The group memory write instruction comprises a plurality of memory write instructions to be executed atomically. The one or more memory write instructions relate to one or more memory addresses associated with memory of the memory module. The method comprises executing the one or more memory write instructions using previously unallocated memory of the memory module. The method comprises obtaining a commit instruction for the group memory write instruction. The method comprises updating the one or more memory addresses based on the previously unallocated memory used for executing the one or more memory write instructions after obtaining the commit instruction for the group memory write instruction.

公开(公告)号：US20190140913A1

公开(公告)日：2019-05-09

申请号：US16235462

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Suraj PRABHAKARAN ,  Kshitij A. DOSHI ,  Brinda GANESH ,  Timothy VERRALL

IPC: H04L12/24 ,  G06N5/04 ,  G06N3/04

Abstract: Examples include techniques for artificial intelligence (AI) capabilities at a network switch. These examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an AI service to be provided by users requesting the AI service.

公开(公告)号：US20190101974A1

公开(公告)日：2019-04-04

申请号：US15721423

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT

IPC: G06F1/32 ,  G06N7/00

Abstract: Examples include techniques to predict memory bandwidth demand for a storage or memory device. Examples include receiving an access request to remotely access a storage device and gather information to use to predict a memory bandwidth demand for subsequent access requests to the storage device. Adjustments to power supplied to the storage device may be caused based on the predicted memory bandwidth demand. The adjustments may load balance power among a plurality of storage devices remotely accessible through a network fabric. The plurality of storage devices including the storage device.

公开(公告)号：US20190042936A1

公开(公告)日：2019-02-07

申请号：US15859472

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Suraj PRABHAKARAN ,  Kshitij A. DOSHI ,  Da-Ming CHIANG

IPC: G06N3/08 ,  G06N5/04

Abstract: Examples include techniques to manage training or trained models for deep learning applications. Examples include routing commands to configure a training model to be implemented by a training module or configure a trained model to be implemented by an inference module. The commands routed via out-of-band (OOB) link while training data for the training models or input data for the trained models are routed via inband links.