公开(公告)号：US20200006322A1

公开(公告)日：2020-01-02

申请号：US16024705

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Paul FISCHER ,  Walid HAFEZ ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L27/06 ,  H01L29/872 ,  H01L21/8252 ,  H01L27/02 ,  H01L29/205 ,  H01L29/20

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393211A1

公开(公告)日：2019-12-26

申请号：US16016419

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Paul FISCHER ,  Walid HAFEZ ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L27/02 ,  H01L29/10 ,  H01L27/06 ,  H01L21/265

Abstract: A substrate contact diode is disclosed. The substrate contact includes a first type substrate implant tap in a substrate, a second type epitaxial implant in an epitaxial layer that is on the substrate, and a first type epitaxial region above the second type epitaxial implant. A contact electrode that extends upward from the top of the first type epitaxial region to the surface of an interlayer dielectric that surrounds the contact electrode.

公开(公告)号：US20190304896A1

公开(公告)日：2019-10-03

申请号：US16462889

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L21/764 ,  H01L29/06

Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines

公开(公告)号：US20190287935A1

公开(公告)日：2019-09-19

申请号：US16345627

申请日：2016-12-21

Applicant: Intel Corporation

Inventor： Paul B. FISCHER ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L23/66 ,  H01L23/14 ,  H01L23/13 ,  H01L23/522 ,  H01L21/50

Abstract: Embodiments of the invention include a microelectronic device that includes an insulating substrate, a RF transistor layer, and an interconnect structure disposed on the RF transistor layer. The RF transistor layer includes RF transistors for microwave frequencies. The interconnect structure includes at least one layer of dielectric material and a conductive layer having a plurality of conductive lines. The insulating substrate reduces parasitic capacitances and parasitic coupling to the insulating substrate.

公开(公告)号：US20190229022A1

公开(公告)日：2019-07-25

申请号：US16372272

申请日：2019-04-01

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Jack KAVALIEROS ,  Willy RACHMADY ,  Van LE ,  Benjamin CHU-KUNG ,  Matthew METZ ,  Robert CHAU

IPC: H01L21/84 ,  H01L21/8258 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/16 ,  H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US20190067081A1

公开(公告)日：2019-02-28

申请号：US16083859

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Seung Hoon SUNG

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L29/20 ,  H01L33/20 ,  H01L33/44

Abstract: A method of fabricating a wafer is disclosed. The method includes forming a protective layer on a device side and a non-device side of a substrate of the wafer. The method further includes removing the protective layer from a center portion of the device side of the substrate while retaining the protective layer in an edge portion of the substrate. The method also includes forming semiconductor layer in the center portion of the device side of the substrate while the protective layer is in the edge portion of the substrate.

公开(公告)号：US20180145052A1

公开(公告)日：2018-05-24

申请号：US15574822

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Peter G. TOLCHINSKY ,  Robert S. CHAU

IPC: H01L25/065 ,  H01L27/06 ,  H01L27/092 ,  H01L23/48 ,  H01L29/20 ,  H01L29/778 ,  H01L25/00 ,  H01L21/8252 ,  H01L21/8238 ,  H01L21/02

Abstract: GaN-On-Silicon (GOS) structures and techniques for accommodating and/or controlling stress/strain incurred during III-N growth on a large diameter silicon substrate. A back-side of a silicon substrate may be processed to adapt substrates of standardized diameters and thicknesses to GOS applications. Bowing and/or warping during high temperature epitaxial growth processes may be mitigated by pre-processing silicon substrate so as to pre-stress the substrate in a manner than counterbalances stress induced by the III-N material and/or improve a substrate's ability to absorb stress. III-N devices fabricated on an engineered GOS substrate may be integrated together with silicon MOS devices fabricated on a separate substrate. Structures employed to improve substrate resilience and/or counterbalance the substrate stress induced by the III-N material may be further employed for interconnecting the III-N and silicon MOS devices of a 3D IC.

公开(公告)号：US20170236928A1

公开(公告)日：2017-08-17

申请号：US15499774

申请日：2017-04-27

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L29/20

CPC classification number: H01L29/7783 ,  H01L21/30612 ,  H01L21/30617 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region.

公开(公告)号：US20160308041A1

公开(公告)日：2016-10-20

申请号：US15036780

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Robert S. CHAU ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Seung Hoon Hoon SUNG ,  Sanaz K. GARDNER ,  Ravi PILLARISETTY

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L29/32 ,  H01L29/34 ,  H01L29/08 ,  H01L29/06 ,  H01L29/205

CPC classification number: H01L29/785 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/0605 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transitors and other transistors can form.

Abstract translation: 公开了在半导体衬底上形成GaN晶体管的技术。 在半导体衬底的顶部形成绝缘层。 填充有包含III-V族半导体材料的沟槽材料的沟槽通过绝缘层形成并延伸到半导体衬底中。 含有缺陷密度低于沟槽材料的III-V材料的沟道结构直接形成在绝缘层的顶部并且与沟槽相邻。 在沟道结构的相对侧上的源极和漏极形式，以及在沟道结构上形成栅极。 半导体衬底形成可以形成GaN移动器和其它晶体管的平面。

公开(公告)号：US20160064512A1

公开(公告)日：2016-03-03

申请号：US14936609

申请日：2015-11-09

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert CHAU ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Matthew METZ ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.