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公开(公告)号：US11515891B2
公开(公告)日：2022-11-29
申请号：US17130697
申请日：2020-12-22
Applicant: Intel Corporation
Inventor： Santhosh K. Vanaparthy , Ravi H. Motwani
Abstract: A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.
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公开(公告)号：US10942799B1
公开(公告)日：2021-03-09
申请号：US16562745
申请日：2019-09-06
Applicant: Intel Corporation
Inventor： Ali Khakifirooz , Pranav Kalavade , Ravi H. Motwani , Chang Wan Ha
Abstract: Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.
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公开(公告)号：US10579473B2
公开(公告)日：2020-03-03
申请号：US15721291
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Santhosh K. Vanaparthy , Ravi H. Motwani , Zion S. Kwok
Abstract: One embodiment provides a silent data corruption (SDC) mitigation circuitry. The SDC mitigation circuitry includes a comparator circuitry and an SDC mitigation logic. The comparator circuitry is to compare a successful decoded codeword and a corresponding received codeword, the successful decoded codeword having been deemed a success by an error correction circuitry. The SDC mitigation logic is to reject the successful decoded codeword if a distance between the corresponding received codeword and the successful decoded codeword is greater than or equal to a threshold.
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公开(公告)号：US09911509B2
公开(公告)日：2018-03-06
申请号：US14099551
申请日：2013-12-06
Applicant: Intel Corporation
Inventor： Ravi H. Motwani
CPC classification number: G11C29/44 , G11C29/42 , G11C29/82 , G11C2029/0409 , G11C2029/0411
Abstract: Methods and apparatus related to utilization of counter(s) for locating faulty die in a distributed codeword storage system are described. In one embodiment, first logic determines a plurality of values. Each of the plurality of values corresponds to a number of zeros or a number of ones in bits read from a portion of each of a plurality of memory dies. Second logic determines one or more candidates as a faulty die amongst the plurality of memory dies based at least in part on a comparison of the plurality of values for the plurality of memory dies. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20170206023A1
公开(公告)日：2017-07-20
申请号：US15001358
申请日：2016-01-20
Applicant: Intel Corporation
Inventor： Ravi H. Motwani
CPC classification number: G06F11/1048 , G06F3/0611 , G06F3/0659 , G06F3/0679 , G06F11/1008 , G06F11/1068 , G11C29/021 , G11C29/28 , G11C29/42 , G11C29/52
Abstract: Technologies for reducing latency in read operations include an apparatus to perform a read attempt of a target data set from a memory, to obtain a candidate data set. A controller performs the read attempt using an initial read parameter, such as an initial read reference voltage. The controller is also to determine a candidate ratio of instances of data values in a portion of the candidate data set, compare the candidate ratio to a predefined reference ratio, determine whether the candidate ratio is within a predefined range of the predefined reference ratio, and, in response to a determination that the candidate ratio is not within the predefined range, adjust the read parameter and perform a subsequent read attempt of the target data set with the adjusted read parameter.
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Patent Agency Ranking
公开(公告)号：US09698830B2
公开(公告)日：2017-07-04
申请号：US13780690
申请日：2013-02-28
Applicant: INTEL CORPORATION
Inventor： Ravi H. Motwani , Kiran Pangal
CPC classification number: H03M13/3715 , H03M13/13 , H03M13/1515 , H03M13/152
Abstract: Embodiments include device, storage media, and methods for decoding a codeword of encoded data. In embodiments, a processor may be coupled with a decoder and configured to multiply the codeword and a parity-check matrix of the encoded data to produce a syndrome. If the syndrome is non-zero then the processor may identify a bit error in the codeword based at least in part on a comparison of the syndrome to one or more columns of the parity-check matrix. Other embodiments may be described and claimed.
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公开(公告)号：US20170186500A1
公开(公告)日：2017-06-29
申请号：US14998240
申请日：2015-12-23
Applicant: INTEL CORPORATION
Inventor： Ravi H. Motwani , Zion S. Kwok , Poovaiah M. Palangappa
CPC classification number: G06F11/1612 , G11C16/26 , G11C29/12 , G11C29/42 , G11C29/4401 , H03M13/05 , H03M13/1102 , H03M13/19 , H03M13/23 , H03M13/2906 , H03M13/2909 , H03M13/2918 , H03M13/2957
Abstract: Memory circuit defect correction in accordance with one aspect of the present description, logically divides a block of data bits into a plurality of data bit sections, each data bit section to be written into and stored in an associated memory section of a block of memory logically divided into a plurality memory sections. In one embodiment, for each data bit section and its associated memory section, the logical values of all the user data bits of the data bit section are selectively flipped so that the logical value of a user data bit to be written into a defective bitcell, matches the fixed read output of a defective bit cell. A bitcell in each memory section may be utilized to set a flip-flag to indicate whether or not the data bits of the memory section have been flipped. Other aspects are described herein.
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公开(公告)号：US20160378594A1
公开(公告)日：2016-12-29
申请号：US14752322
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Ravi H. Motwani
CPC classification number: G11C29/52 , G06F11/1012 , G11C2029/0411 , H03M13/1108 , H03M13/1171
Abstract: Apparatus, systems, and methods for recovery algorithm in memory are described. In one embodiment a memory comprises a memory device and a controller coupled to the memory device and comprising logic, at least partially including hardware logic, to in response to a read request received from a host device, retrieve data from the memory device, perform an error correction code (ECC) check on the data retrieved from the memory device, invoke a recovery operation in response to an ECC error, wherein the recovery operation performs a non-binary, iterative symbol flipping procedure. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了用于存储器中的恢复算法的装置，系统和方法。 在一个实施例中，存储器包括存储器设备和耦合到存储器设备的控制器，并且包括至少部分地包括硬件逻辑的逻辑，以响应从主机设备接收到的读取请求，从存储器设备检索数据，执行 对从存储器件检索的数据进行纠错码（ECC）检查，响应于ECC错误来调用恢复操作，其中恢复操作执行非二进制的迭代符号翻转过程。 还公开并要求保护其他实施例。
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59.发明授权Using read values from previous decoding operations to calculate soft bit information in an error recovery operation 有权使用先前解码操作中的读取值来计算错误恢复操作中的软位信息公开(公告)号：US09298552B2
公开(公告)日：2016-03-29
申请号：US14040554
申请日：2013-09-27
Applicant: Intel Corporation
Inventor： Lark-Hoon Leem , Xin Guo , Ravi H. Motwani , Rosanna Yee , Scott E. Nelson
CPC classification number: G06F11/141 , G06F11/1012
Abstract: Provided are an apparatus, system, and method for performing an error recovery operation with respect to a read of a block of memory cells in a storage device. A current iteration of a decoding operation is performed by applying at least one reference voltage for the current iteration to a block of the memory cells in the storage device to determine current read values in response to applying the reference voltage. A symbol is generated for each of the read memory cells by combining the determined current read value with at least one value saved during the previous iteration. The symbols are used to determine bit reliability metrics for the block of memory cells. The bit reliability metrics are decoded. In response to the decoding failing, an additional iteration of the decoding operation is performed.
Abstract translation: 提供了一种用于对存储装置中的存储单元块的读取执行错误恢复操作的装置，系统和方法。 通过对当前迭代中的至少一个参考电压施加到存储装置中的存储器单元的块来执行解码操作的当前迭代，以响应于施加参考电压来确定当前读取值。 通过将确定的当前读取值与在先前迭代中保存的至少一个值组合，为每个读取的存储器单元生成符号。 这些符号用于确定存储器单元块的位可靠性度量。 比特可靠性度量被解码。 响应于解码失败，执行解码操作的附加迭代。
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60.发明授权Multi-level cell (MLC) non-volatile memory data reading method and apparatus 有权多级单元（MLC）非易失性存储器数据读取方法和装置公开(公告)号：US09093170B2
公开(公告)日：2015-07-28
申请号：US13782821
申请日：2013-03-01
Applicant: Intel Corporation
Inventor： Ravi H. Motwani
CPC classification number: G11C13/004 , G06F3/0608 , G06F3/0661 , G06F3/0679 , G11C11/5642 , G11C11/5678 , G11C16/26
Abstract: Embodiments include systems, methods, and apparatuses for reading the signal-level of three-signal-level cells in a non-volatile memory (NVM). In one embodiment, a receiver may be configured to receive a serial string of values and identify which values in the string are the results of a lower-page read or an upper-page read of the cells. In some embodiments, one signal-level of a three-signal level cell may be represented only by a value in the lower-page read of the cells, while a second signal-level of the three-signal level cell may be represented by a value in the lower-page read of the cells and an upper-page read of the cells.
Abstract translation: 实施例包括用于读取非易失性存储器（NVM）中的三信号电平单元的信号电平的系统，方法和装置。 在一个实施例中，接收器可以被配置为接收串行串的值并且识别字符串中的哪些值是小区读取的低页面读取或高字节读取的结果。 在一些实施例中，三信号电平单元的一个信号电平可以仅由单元的较低页面读取中的值表示，而三信号电平单元的第二信号电平可由 单元格的低页面读取中的值和单元格的上页读取。
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