公开(公告)号：US20230275135A1

公开(公告)日：2023-08-31

申请号：US18131336

申请日：2023-04-05

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK ,  Kimin JUN

IPC: H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L27/1266 ,  H01L29/78 ,  H01L29/401 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66803 ,  H01L21/2254 ,  H01L29/66545

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20220285342A1

公开(公告)日：2022-09-08

申请号：US17825664

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Yih WANG ,  Rishabh MEHANDRU ,  Mauro J. KOBRINSKY ,  Tahir GHANI ,  Mark BOHR ,  Marni NABORS

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

公开(公告)号：US20220115372A1

公开(公告)日：2022-04-14

申请号：US17555296

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Patrick MORROW ,  Gilbert DEWEY ,  Willy RACHMADY ,  Rishabh MEHANDRU

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L27/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/822

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.

公开(公告)号：US20210057413A1

公开(公告)日：2021-02-25

申请号：US16954126

申请日：2018-03-28

Applicant: Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Intel Corporation

Inventor： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ

IPC: H01L27/092 ,  H01L21/822 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20200303238A1

公开(公告)日：2020-09-24

申请号：US16358520

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Hui Jae YOO ,  Patrick MORROW ,  Kevin LIN

IPC: H01L21/768 ,  H01L29/417 ,  H01L21/762 ,  H01L21/683 ,  H01L23/31

Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20200279872A1

公开(公告)日：2020-09-03

申请号：US16649593

申请日：2018-01-12

Applicant: INTEL CORPORATION

Inventor： Dipanjan BASU ,  Rishabh MEHANDRU ,  Seung Hoon SUNG

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L21/84

Abstract: An apparatus is provided which comprises: a source and a drain with a semiconductor body therebetween, the source, the drain, and the semiconductor body on an insulator, a buried structure between the semiconductor body and the insulator, and a source contact coupled with the source and the buried structure, the source contact comprising metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200035560A1

公开(公告)日：2020-01-30

申请号：US16316330

申请日：2017-08-25

Applicant: Intel Corporation

Inventor： Bruce BLOCK ,  Valluri R. RAO ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Doug INGERLY ,  Kimin JUN ,  Kevin O'BRIEN ,  Patrick MORROW ,  Szyua S. LIAO

IPC: H01L21/822 ,  H01L29/04 ,  H01L29/08 ,  H01L23/528 ,  H01L23/00 ,  H01L29/16 ,  H01L29/20 ,  H01L27/092 ,  H01L27/12 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/683 ,  H01L29/06 ,  H01L21/66

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

公开(公告)号：US20200013905A1

公开(公告)日：2020-01-09

申请号：US16578004

申请日：2019-09-20

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Szuya S. LIAO ,  Stephen M. CEA

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

Abstract: Semiconductor nanowire devices having cavity spacers and methods of fabricating cavity spacers for semiconductor nanowire devices are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires including a discrete channel region. A common gate electrode stack surrounds each of the discrete channel regions of the plurality of vertically stacked nanowires. A pair of dielectric spacers is on either side of the common gate electrode stack, each of the pair of dielectric spacers including a continuous material disposed along a sidewall of the common gate electrode and surrounding a discrete portion of each of the vertically stacked nanowires. A pair of source and drain regions is on either side of the pair of dielectric spacers.

公开(公告)号：US20200006573A1

公开(公告)日：2020-01-02

申请号：US16022480

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Van H. LE ,  Abhishek A. SHARMA ,  Tahir GHANI ,  Rishabh MEHANDRU ,  Gilbert DEWEY ,  Willy RACHMADY

IPC: H01L29/786 ,  H01L29/423

Abstract: Double gated thin film transistors are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate electrode is on the insulator layer, the first gate electrode having a non-planar feature. A first gate dielectric is on and conformal with the non-planar feature of the first gate electrode. A channel material layer is on and conformal with the first gate dielectric. A second gate dielectric is on and conformal with the channel material layer. A second gate electrode is on and conformal with the second gate dielectric. A first source or drain region is coupled to the channel material layer at a first side of the first gate dielectric. A second source or drain region is coupled to the channel material layer at a second side of the first gate dielectric.

公开(公告)号：US20190237466A1

公开(公告)日：2019-08-01

申请号：US16318361

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Patrick H. KEYS ,  Hei KAM ,  Rishabh MEHANDRU ,  Aaron A. BUDREVICH

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/167 ,  H01L29/43 ,  H01L29/49 ,  H01L29/66795 ,  H01L29/785

Abstract: A transistor including a gate stack and source and drain on opposing sides of the gate stack; and a first material and a second material on the substrate, the first material disposed between the substrate and the second material and the channel of the transistor is defined in the second material between the source and drain, wherein the first material and the second material each include an implant and the implant includes a greater solubility in the first material than in the second material. A method for forming an integrated circuit structure including forming a first material on a substrate; forming a second material on the first material; introducing an implant into the second material, wherein the implant includes a greater solubility in the first material than in the second material; annealing the substrate; and forming a transistor on the substrate, the transistor including a channel including the second material.