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    Encapsulated sensors
    51.
    发明授权
    Encapsulated sensors 有权
    封装传感器

    公开(公告)号：US09171971B2

    公开(公告)日：2015-10-27

    申请号：US14068461

    申请日：2013-10-31

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  William J. Murphy ,  Kirk D. Peterson ,  Steven M. Shank

    IPC: H01L31/0203 ,  H01L31/20

    CPC classification number: H01L31/0203 ,  H01L31/1872 ,  H01L31/208 ,  Y02E10/50 ,  Y02P70/521

    Abstract: An encapsulated sensors and methods of manufacture are disclosed herein. The method includes forming an amorphous or polycrystalline material in contact with a layer of seed material. The method further includes forming an expansion space for the amorphous or polycrystalline material. The method further includes forming an encapsulation structure about the amorphous or polycrystalline material. The method further includes crystallizing the amorphous or polycrystalline material by a thermal anneal process such that the amorphous or polycrystalline material expands within the expansion space.

    Abstract translation: 封装的传感器和制造方法在本文中公开。 该方法包括形成与种子材料层接触的无定形或多晶材料。 该方法还包括形成用于非晶或多晶材料的膨胀空间。 该方法还包括形成关于非晶或多晶材料的封装结构。 该方法还包括通过热退火工艺使非晶或多晶材料结晶，使得非晶或多晶材料在膨胀空间内膨胀。

    High linearity SOI wafer for low-distortion circuit applications
    52.
    发明授权
    High linearity SOI wafer for low-distortion circuit applications 有权
    用于低失真电路应用的高线性SOI晶片

    公开(公告)号：US09165819B2

    公开(公告)日：2015-10-20

    申请号：US14546058

    申请日：2014-11-18

    Applicant: International Business Machines Corporation

    Inventor： Alan B. Botula ,  Jeffrey E. Hanrahan ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Dale W. Martin ,  Gerd Pfeiffer ,  James A. Slinkman

    IPC: H01L21/76 ,  H01L21/04 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324

    CPC classification number: H01L21/76251 ,  H01L21/04 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324

    Abstract: According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.

    Abstract translation: 根据本文的方法，在第一材料被植入之后，衬底的第一侧被注入第一材料，以将衬底的第一侧的结晶结构从第一结晶状态改变到第二结晶状态。 在植入第一种材料之后，第二种材料沉积在基底的第一面上。 绝缘体层的第一面在衬底的第一侧上与第二材料接合。 在绝缘体层与第二材料结合之后，在绝缘体层的与绝缘体层的第一侧相对的第二侧上形成集成电路器件。 集成电路器件进行热退火。 第一种材料在退火过程中保持衬底的第一面的第二结晶状态。

    High resistivity silicon-on-insulator substrate and method of forming
    53.
    发明授权
    High resistivity silicon-on-insulator substrate and method of forming 有权
    高电阻率硅绝缘体基板及其成型方法

    公开(公告)号：US08963293B2

    公开(公告)日：2015-02-24

    申请号：US14151582

    申请日：2014-01-09

    Applicant: International Business Machines Corporation

    Inventor： Alan B. Botula ,  Mark D. Jaffe ,  Alvin J. Joseph

    IPC: H01L23/58 ,  H01L29/16 ,  H01L21/762

    CPC classification number: H01L29/16 ,  H01L21/76254

    Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.

    Abstract translation: 半导体结构及其形成方法。 在一个实施例中，形成绝缘体上硅（SOI）晶片衬底的方法包括：提供处理衬底; 在所述手柄衬底上形成高电阻率材料层，所述高电阻率材料层包括非晶碳化硅（SiC），多晶SiC，无定形金刚石或多晶金刚石中的一种; 在所述高电阻率材料层上形成绝缘体层; 并将施主晶片接合到绝缘体层的顶表面以形成SOI晶片衬底。

    VERTICALLY CURVED WAVEGUIDE
    55.
    发明申请
    VERTICALLY CURVED WAVEGUIDE 有权
    垂直弯曲波形

    公开(公告)号：US20140321802A1

    公开(公告)日：2014-10-30

    申请号：US13872396

    申请日：2013-04-29

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Kirk D. Peterson ,  Jed H. Rankin

    IPC: G02B6/122 ,  G02B6/13

    CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B6/136 ,  G02B6/4214

    Abstract: An optical waveguide structure may include an optical waveguide structure located within a semiconductor structure and an optical coupler. The optical coupler may include a metallic structure located within an electrical interconnection region of the semiconductor structure, whereby the metallic structure extends downward in a substantially curved shape from a top surface of the electrical interconnection region and couples to the optical waveguide structure. The optical coupler may further include an optical signal guiding region bounded within the metallic structure, whereby the optical coupler receives an optical signal from the top surface and couples the optical signal to the optical waveguide structure such that the optical signal propagation is substantially vertical at the top surface and substantially horizontal at the optical waveguide structure.

    Abstract translation: 光波导结构可以包括位于半导体结构内的光波导结构和光耦合器。 光耦合器可以包括位于半导体结构的电互连区域内的金属结构，由此金属结构从电互连区域的顶表面以基本弯曲的形状向下延伸并且耦合到光波导结构。 光耦合器还可以包括在金属结构内限定的光信号引导区域，由此光耦合器从顶表面接收光信号并将光信号耦合到光波导结构，使得光信号传播在 顶表面并且在光波导结构处基本上水平。

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