公开(公告)号：US11152464B1

公开(公告)日：2021-10-19

申请号：US16832047

申请日：2020-03-27

Applicant: International Business Machines Corporation

Inventor： Balasubramanian S. Pranatharthi Haran ,  Ruilong Xie ,  Veeraraghavan S. Basker ,  Robert Robison

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/10

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having self-aligned isolations. In a non-limiting embodiment of the invention, a first gate stack is formed over channel regions of a first nanosheet stack. A second gate stack is formed over channel regions of a second nanosheet stack adjacent to the first nanosheet stack. An isolation pillar is positioned between the first gate stack and the second gate stack. The isolation pillar includes a top portion having a first width and a bottom portion having a second width less than the first width.

公开(公告)号：US11152257B2

公开(公告)日：2021-10-19

申请号：US16744254

申请日：2020-01-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Hosadurga Shobha ,  Junli Wang ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Robert Robison ,  Huai Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method for fabricating a semiconductor device includes forming one or more layers including at least one of a liner and a barrier along surfaces of a first interlevel dielectric (ILD) layer within a trench, after forming the one or more liners, performing a via etch to form a via opening exposing a first conductive line corresponding to a first metallization level, and forming, within the via opening and on the first conductive line, a barrier-less prefilled via including first conductive material.

公开(公告)号：US11139201B2

公开(公告)日：2021-10-05

申请号：US16672904

申请日：2019-11-04

Applicant: International Business Machines Corporation

Inventor： Koichi Motoyama ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Somnath Ghosh ,  Robert Robison ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3213

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures for subtractively forming a top via using a hybrid metallization scheme. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a topmost surface of a first liner layer. The first liner layer can be positioned between the conductive line and a dielectric layer. A top via layer is formed on the recessed surface of the conductive line and a hard mask is formed over a first portion of the top via layer. A second portion of the top via layer is removed. The remaining first portion of the top via layer defines the top via. The conductive line can include copper while the top via layers can include ruthenium or cobalt.

公开(公告)号：US20210305089A1

公开(公告)日：2021-09-30

申请号：US16828551

申请日：2020-03-24

Applicant: International Business Machines Corporation

Inventor： Timothy Mathew Philip ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/528

Abstract: A method includes forming a dielectric layer on a semiconductor substrate, forming a first mandrel layer and a second mandrel layer on the dielectric layer and patterning the first mandrel layer and the second mandrel layer to form respective first and second patterns in the first and second mandrel layers. The first pattern includes a first line segment and a first wing segment. The first wing segment is filled with a first spacer material to form a first spacer. The method further includes removing exposed portions of the first and second mandrel layers, transferring an image of the first and second patterns, patterning the dielectric layer and depositing a metal into the patterned dielectric layer to form a metallic interconnect structure. The metallic interconnect structure includes first and second metallic lines with the second metallic line having a line break corresponding to the first spacer.

公开(公告)号：US20210296171A1

公开(公告)日：2021-09-23

申请号：US16821428

申请日：2020-03-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Robert Robison

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/04

Abstract: A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.

公开(公告)号：US20210233807A1

公开(公告)日：2021-07-29

申请号：US16750040

申请日：2020-01-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Nicholas Anthony Lanzillo ,  Kisik Choi ,  Robert Robison

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/02

Abstract: Integrated chips and methods of forming the same include forming conductive lines on an underlying layer, between regions of dielectric material. The regions of dielectric material are selectively patterned, leaving at least one dielectric remnant region. An interlayer dielectric is formed over the underlying layer and the at least one dielectric remnant region, between the conductive lines.

公开(公告)号：US20210225700A1

公开(公告)日：2021-07-22

申请号：US16744254

申请日：2020-01-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Hosadurga Shobha ,  Junli Wang ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Robert Robison ,  Huai Huang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: A method for fabricating a semiconductor device includes forming one or more layers including at least one of a liner and a barrier along surfaces of a first interlevel dielectric (ILD) layer within a trench, after forming the one or more liners, performing a via etch to form a via opening exposing a first conductive line corresponding to a first metallization level, and forming, within the via opening and on the first conductive line, a barrier-less prefilled via including first conductive material.

公开(公告)号：US20210013321A1

公开(公告)日：2021-01-14

申请号：US16504739

申请日：2019-07-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Yogendra ,  Ardasheir Rahman ,  Robert Robison ,  Adra Carr

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L27/092

Abstract: Semiconductor devices and methods of forming the same include forming a dummy gate on a stack of alternating channel layers and sacrificial layers. A spacer layer is formed over the dummy gate and the stack. Portions of the spacer layer on horizontal surfaces of the stack are etched away to form vertical spacers. Exposed portions of the stack are etched away. Semiconductor material is grown from exposed sidewalls of remaining channel layers to form source and drain structures that are constrained in lateral dimensions by the vertical spacers.

公开(公告)号：US12243819B2

公开(公告)日：2025-03-04

申请号：US17873888

申请日：2022-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent Alan Anderson ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Robert Robison

IPC: H01L23/528 ,  H01L21/768

Abstract: Integrated chips include first lines, formed on an underlying substrate. Spacers are formed conformally on sidewalls of the plurality of lines. Etch stop remnants are positioned on the sidewalls of the plurality of lines, between the spacers and the underlying substrate. Second lines are formed on the underlying substrate, between respective pairs of adjacent first lines.

公开(公告)号：US11990410B2

公开(公告)日：2024-05-21

申请号：US17495980

申请日：2021-10-07

Applicant: International Business Machines Corporation

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Kisik Choi ,  Robert Robison

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/5226

Abstract: A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.