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    DUAL CHANNEL HYBRID SEMICONDUCTOR-ON-INSULATOR SEMICONDUCTOR DEVICES
    51.
    发明申请
    DUAL CHANNEL HYBRID SEMICONDUCTOR-ON-INSULATOR SEMICONDUCTOR DEVICES 有权
    双通道混合半导体绝缘体半导体器件

    公开(公告)号：US20150279861A1

    公开(公告)日：2015-10-01

    申请号：US14739736

    申请日：2015-06-15

    Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc. ,  Commissariat A I'Energie atomique et aux Energies alternatives

    Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Laurent Grenouillet ,  Yannick Le Tiec ,  Maud Vinet

    IPC: H01L27/12 ,  H01L29/16 ,  H01L29/06 ,  H01L29/161

    CPC classification number: H01L27/1207 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161

    Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal. Within each of the SOI region and the bulk region, two types of semiconductor material portions are formed depending on whether a semiconductor material intermixes with the semiconductor alloy material.

    Abstract translation: 通过顶部半导体层和绝缘体上半导体（SOI）衬底的掩埋绝缘体层形成沟槽。 执行选择性外延以形成填充沟槽并与处理衬底的半导体材料外延对准的体半导体部分。 在顶部半导体层和体半导体部分上沉积至少一个电介质层，并且被图案化以在顶部半导体层和体半导体部分的选定区域上形成开口。 半导体合金材料直接在顶部半导体层和体半导体部分的物理暴露表面上沉积在开口内。 半导体合金材料在随后的退火中与下面的半导体材料混合。 在SOI区域和体区域的每一个内，根据半导体材料是否与半导体合金材料混合形成两种类型的半导体材料部分。

    METHOD FOR THE FORMATION OF A PROTECTIVE DUAL LINER FOR A SHALLOW TRENCH ISOLATION STRUCTURE
    53.
    发明申请
    METHOD FOR THE FORMATION OF A PROTECTIVE DUAL LINER FOR A SHALLOW TRENCH ISOLATION STRUCTURE 有权
    用于形成用于浅层隔离结构的保护性双层衬垫的方法

    公开(公告)号：US20140357039A1

    公开(公告)日：2014-12-04

    申请号：US13907237

    申请日：2013-05-31

    Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

    Inventor： Qing Liu ,  Nicolas Loubet ,  Bruce Doris

    IPC: H01L21/762 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L29/66477 ,  H01L21/76232 ,  H01L21/76283 ,  H01L29/0649

    Abstract: On a substrate formed of a first semiconductor layer, an insulating layer and a second semiconductor layer, a silicon oxide pad layer and a silicon nitride pad layer are deposited and patterned to define a mask. The mask is used to open a trench through the first semiconductor layer and insulating layer and into the second semiconductor layer. A dual liner of silicon dioxide and silicon nitride is conformally deposited within the trench. The trench is filled with silicon dioxide. A hydrofluoric acid etch removes the silicon nitride pad layer along with a portion of the conformal silicon nitride liner. A hot phosphoric acid etch removes the silicon oxide pad layer, a portion of the silicon oxide filling the trench and a portion of the conformal silicon nitride liner. The dual liner protects against substrate etch through at an edge of the trench between the first and second semiconductor layers.

    Abstract translation: 在由第一半导体层，绝缘层和第二半导体层形成的衬底上，沉积氧化硅衬垫层和氮化硅衬垫层以形成掩模。 掩模用于打开通过第一半导体层和绝缘层并进入第二半导体层的沟槽。 二氧化硅和氮化硅的双衬垫共形沉积在沟槽内。 沟槽填充有二氧化硅。 氢氟酸蚀刻将氮化硅衬垫层与一部分共形氮化硅衬垫一起去除。 热磷酸蚀刻去除氧化硅衬垫层，填充沟槽的氧化硅的一部分和保形氮化硅衬垫的一部分。 双衬垫在第一和第二半导体层之间的沟槽的边缘处防止衬底蚀刻。

    MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS AND RELATED METHODS
    56.
    发明申请
    MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS AND RELATED METHODS 有权
    具有多个介电栅堆叠的存储器件及相关方法

    公开(公告)号：US20140291749A1

    公开(公告)日：2014-10-02

    申请号：US13852645

    申请日：2013-03-28

    Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Prasanna KHARE ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

    IPC: H01L29/423 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

    Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域和栅极堆叠。 栅极堆叠可以包括沟道区域上的第一介电层，第一介电层上的第一扩散阻挡层，第一扩散阻挡层上的第一导电层，第一导电层上的第二介电层，第二介电层 第二介电层上的扩散阻挡层，以及位于第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。

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