公开(公告)号：US20200183688A1

公开(公告)日：2020-06-11

申请号：US16788285

申请日：2020-02-11

申请人： Intel Corporation

发明人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal San Andrian ,  Elmoustapha Ould-Ahmed Vall ,  Mark J. Charney

IPC分类号： G06F9/30

摘要： A method of an aspect includes receiving a packed data operation mask shift instruction. The packed data operation mask shift instruction indicates a source having a packed data operation mask, indicates a shift count number of bits, and indicates a destination. The method further includes storing a result in the destination in response to the packed data operation mask shift instruction. The result includes a sequence of bits of the packed data operation mask that have been shifted by the shift count number of bits. Other methods, apparatus, systems, and instructions are disclosed.

公开(公告)号：US10649774B2

公开(公告)日：2020-05-12

申请号：US15855575

申请日：2017-12-27

申请人： Intel Corporation

发明人： Vinodh Gopal ,  James D. Guilford ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Gilbert M. Wolrich ,  Martin G. Dixon ,  Mark C. Davis ,  Sean P. Mirkes ,  Alexandre J. Farcy ,  Bret L. Toll ,  Maxim Loktyukhin

IPC分类号： G06F9/30

摘要： A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

公开(公告)号：US10282296B2

公开(公告)日：2019-05-07

申请号：US15376647

申请日：2016-12-12

申请人： Intel Corporation

发明人： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Elmoustapha Ould-Ahmed-Vall ,  Bret L. Toll ,  David Papworth ,  James D. Allen

IPC分类号： G06F12/0831 ,  G06F12/1009 ,  G06F12/1027

摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US10089229B2

公开(公告)日：2018-10-02

申请号：US15401220

申请日：2017-01-09

申请人： Intel Corporation

发明人： Andrew J. Herdrich ,  Edwin Verplanke ,  Ravishankar Iyer ,  Christopher C. Gianos ,  Jeffrey D. Chamberlain ,  Ronak Singhal ,  Julius Mandelblat ,  Bret L. Toll

IPC分类号： G06F12/08 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0897

摘要： Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

公开(公告)号：US20180136936A1

公开(公告)日：2018-05-17

申请号：US15855575

申请日：2017-12-27

申请人： Intel Corporation

发明人： Vinodh Gopal ,  James D. Guilford ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Gilbert M. Wolrich ,  Martin G. Dixon ,  Mark C. Davis ,  Sean P. Mirkes ,  Alexandre J. Farcy ,  Bret L. Toll ,  Maxim Loktyukhin

IPC分类号： G06F9/30

CPC分类号： G06F9/30094 ,  G06F9/30014

摘要： A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

公开(公告)号：US09946540B2

公开(公告)日：2018-04-17

申请号：US15601960

申请日：2017-05-22

申请人： Intel Corporation

发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/30029 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109

摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

公开(公告)号：US09665368B2

公开(公告)日：2017-05-30

申请号：US13631666

申请日：2012-09-28

申请人： Intel Corporation

发明人： Christopher J. Hughes ,  Mark J. Charney ,  Jesus Corbal ,  Milind B. Girkar ,  Elmoustapha Ould-Ahmed_Vall ,  Bret L. Toll ,  Robert Valentine

IPC分类号： G06F9/30

CPC分类号： G06F9/3001 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109

摘要： Systems, apparatuses, and methods of performing in a computer processor broadcasting data in response to a single vector packed broadcasting instruction that includes a source writemask register operand, a destination vector register operand, and an opcode. In some embodiments, the data of the source writemask register is zero extended prior to broadcasting.

公开(公告)号：US20170024206A1

公开(公告)日：2017-01-26

申请号：US15169297

申请日：2016-05-31

申请人： Intel Corporation

发明人： Bret L. Toll ,  Robert Valentine ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Mark J. Charney

IPC分类号： G06F9/30

CPC分类号： G06F9/30018 ,  G06F9/30025 ,  G06F9/30098 ,  G06F9/30181

摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor mask bit compression in response to a single mask bit compression instruction that includes a source writemask register operand, a destination writemask register operand, and an opcode are described.

摘要翻译： 描述了在计算机处理器中执行屏蔽位压缩的系统，装置和方法的实施例，其响应于包括源写入寄存器操作数，目的地写入寄存器操作数和操作码的单个掩码位压缩指令。

公开(公告)号：US09501276B2

公开(公告)日：2016-11-22

申请号：US13731809

申请日：2012-12-31

申请人： Intel Corporation

发明人： Tal Uliel ,  Elmoustapha Ould-Ahmed-Vall ,  Bret L. Toll

IPC分类号： G06F15/76 ,  G06F9/30

CPC分类号： G06F9/30036 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/3016 ,  G06F15/8007

摘要： Instructions and logic provide vectorization of conditional loops. A vector expand instruction has a parameter to specify a source vector, a parameter to specify a conditions mask register, and a destination parameter to specify a destination vector to hold n consecutive vector elements, each of the plurality of n consecutive vector elements having a same variable partition size of m bytes. In response to the processor instruction, data is copied from consecutive vector elements in the source vector, and expanded into unmasked vector elements of the specified destination vector, without copying data into masked vector elements of the destination vector, wherein n varies responsive to the processor instruction executed. The source vector may be a register and the destination vector may be in memory. Some embodiments store counts of the condition decisions. Alternative embodiments may store other data, for example such as target addresses, or table offsets, or indicators of processing directives, etc.

摘要翻译： 指令和逻辑提供条件循环的向量化。 矢量展开指令具有指定源矢量的参数，用于指定条件屏蔽寄存器的参数和用于指定保持n个连续矢量元素的目的地矢量的目的地参数，所述多个n个连续矢量元素中的每一个具有相同的矢量元素 可变分区大小为m字节。 响应于处理器指令，从源向量中的连续向量元素复制数据，并将其扩展到指定目标向量的未屏蔽向量元素，而不将数据复制到目标向量的被掩蔽向量元素中，其中n响应于处理器 执行指令 源向量可以是寄存器，并且目的地向量可以在存储器中。 一些实施例存储条件决定的计数。 替代实施例可以存储其他数据，例如目标地址或表偏移，或处理指令的指示符等。

公开(公告)号：US20160266992A1

公开(公告)日：2016-09-15

申请号：US14998055

申请日：2015-12-24

申请人： Intel Corporation

发明人： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC分类号： G06F11/28 ,  G06F9/30 ,  G06F11/14 ,  G06F12/08 ,  G11C7/10 ,  G06F11/25 ,  G06F9/46 ,  G06F9/38

CPC分类号： G06F11/28 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/466 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/2236 ,  G06F11/25 ,  G06F11/263 ,  G06F12/0811 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1032 ,  G06F2212/20 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/608 ,  G06F2212/621 ,  G11C7/1072

摘要： Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.