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    LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
    51.
    发明申请
    LOCALIZED HIGH DENSITY SUBSTRATE ROUTING 有权

    公开(公告)号：US20230130944A1

    公开(公告)日：2023-04-27

    申请号：US18089213

    申请日：2022-12-27

    Applicant: Intel Corporation

    Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

    IPC: H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

    LOW COST PACKAGE WARPAGE SOLUTION
    53.
    发明申请
    LOW COST PACKAGE WARPAGE SOLUTION 有权

    公开(公告)号：US20220230892A1

    公开(公告)日：2022-07-21

    申请号：US17715923

    申请日：2022-04-07

    Applicant: Intel Corporation

    Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

    IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/16

    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

    NESTED INTERPOSER PACKAGE FOR IC CHIPS
    55.
    发明申请
    NESTED INTERPOSER PACKAGE FOR IC CHIPS 有权

    公开(公告)号：US20210005542A1

    公开(公告)日：2021-01-07

    申请号：US16502622

    申请日：2019-07-03

    Applicant: Intel Corporation

    Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM

    IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

    Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises an interposer, where the interposer comprises a cavity that passes through the interposer, a through interposer via (TIV), and an interposer pad electrically coupled to the TIV. In an embodiment, the electronic package further comprises a nested component in the cavity, where the nested component comprises a component pad, and a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect. In an embodiment, the first interconnect and the second interconnect each comprise an intermediate pad, and a bump over the intermediate pad.

    CORELESS ARCHITECTURE AND PROCESSING STRATEGY FOR EMIB-BASED SUBSTRATES WITH HIGH ACCURACY AND HIGH DENSITY
    56.
    发明申请
    CORELESS ARCHITECTURE AND PROCESSING STRATEGY FOR EMIB-BASED SUBSTRATES WITH HIGH ACCURACY AND HIGH DENSITY 审中-公开

    公开(公告)号：US20200335443A1

    公开(公告)日：2020-10-22

    申请号：US16387167

    申请日：2019-04-17

    Applicant: Intel Corporation

    Inventor： Xiao Di SUN ZHOU ,  Debendra MALLIK ,  Xiaoying GUO

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683

    Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a plurality of conductive layers over a package substrate. The conductive layers include a first conductive layer and first-level interconnects (FLIs) in the package substrate. The semiconductor package also includes a solder resist that surrounds the FLIs, where the solder resist has a top surface that is substantially coplanar to top surfaces of the FLIs, a bridge coupled directly to the first conductive layer with solder balls, where the first conductive layer is coupled to the FLIs, and a dielectric over the conductive layers, the bridge, and the solder resist of the package substrate. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first conductive layer may include first conductive pads and second conductive pads. The FLIs may include first conductive vias, second conductive vias, diffusion layers, and third conductive pads.

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