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公开(公告)号：US10833204B2
公开(公告)日：2020-11-10
申请号：US16591873
申请日：2019-10-03
发明人： Kangguo Cheng , Lawrence A. Clevenger , Carl Radens , Junli Wang , John H. Zhang
IPC分类号： H01L29/786 , H01L29/06 , H01L29/423 , H01L27/088 , H01L29/66 , H01L29/40 , H01L29/417
摘要： A technique relates to a semiconductor device. A first stack includes a first plurality of nanowires respectively coupled to first source and drain regions, and a second stack includes a second plurality of nanowires respectively coupled to second source and drain regions. First source and drain contacts couple to a first predefined number of the first plurality of nanowires. Second source and drain contacts to couple to a second predefined number of the second plurality of nanowires, wherein the first predefined number is different from the second predefined number.
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公开(公告)号：US10832916B1
公开(公告)日：2020-11-10
申请号：US16511640
申请日：2019-07-15
IPC分类号： H01L21/00 , H01L27/00 , H01L29/00 , H01L21/28 , H01L21/8238 , H01L27/11 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66 , H01L21/02
摘要： A method of forming a semiconductor structure includes forming fins over a substrate, forming a shallow trench isolation region over the substrate surrounding the fins, and forming nanosheet stacks providing channels for nanosheet field-effect transistors. The method also includes forming a channel protecting liner over a portion of sidewalls and a top surface of a first nanosheet stack formed over a first fin, the channel protecting liner being further formed over a portion of the shallow trench isolation region extending from the sidewalls of the first nanosheet stack toward a second nanosheet stack formed over a second fin. The method further includes forming gate stacks surrounding exposed portions of the nanosheet stacks, forming an asymmetric self-aligned gate isolation structure over the channel protecting liner, and forming a symmetric self-aligned gate isolation structure over a portion of the shallow trench isolation region between a third fin and a fourth fin.
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公开(公告)号：US20200006561A1
公开(公告)日：2020-01-02
申请号：US16539294
申请日：2019-08-13
发明人： Kangguo Cheng , JUNLI WANG , Lawrence A. Clevenger , Carl Radens , John H. Zhang
IPC分类号： H01L29/78 , H01L27/088 , H01L27/092 , H01L21/762 , H01L29/66
摘要： A semiconductor device is formed to include a fin structure, a first trench at a first lateral end of the fin, a second trench at a second lateral end of the fin, and a filler filled on a first traverse side of the fin and a second traverse side of the fin. The filler is contained between the first trench and the second trench, and oxidized in-place to cause a stress to be exerted on the first and second traverse sides of the fin, the stress causing the fin to exhibit a tensile strain in a lateral running direction of the fin.
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公开(公告)号：US10438850B1
公开(公告)日：2019-10-08
申请号：US16042585
申请日：2018-07-23
发明人： Kangguo Cheng , Lawrence A. Clevenger , Carl Radens , Junli Wang , John H. Zhang
IPC分类号： H01L21/70 , H01L21/768 , H01L27/092 , H01L21/8238
摘要： A first TS is coupled to first S/D over first fin, second TS coupled to second S/D over first fin, third TS coupled to third S/D over second fin, fourth TS coupled to fourth S/D over second fin, gate metal over first and second fins, and gate cap over gate metal. First TS cap is on first TS, second TS cap on second TS, third TS cap on third TS, and fourth TS cap on fourth TS. ILD is formed on top of gate cap and first through fourth TS caps. First opening is through ILD and second TS cap such that part of gate metal is exposed, after removing part of gate cap. Second opening is through ILD to expose another part of gate metal. Combined gate metal contact and local metal connection is formed in first opening and individual gate metal contact is formed in second opening.
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公开(公告)号：US10431495B1
公开(公告)日：2019-10-01
申请号：US16042561
申请日：2018-07-23
发明人： Kangguo Cheng , Lawrence A. Clevenger , Carl Radens , Junli Wang , John H. Zhang
IPC分类号： H01L21/768 , H01L29/66 , H01L21/8238 , H01L27/092
摘要： A technique relates to a semiconductor device. A first trench silicide (TS) is coupled to a first source or drain (S/D). A second TS is coupled to a second S/D, and a gate metal is separated from the first and second TS. A trench is formed above and on sides of the gate metal. A local connection metal is formed in the trench such that the gate metal is coupled to the first TS and the second TS. A local connection cap is formed on top of the local connection metal.
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公开(公告)号：US09905511B2
公开(公告)日：2018-02-27
申请号：US14937812
申请日：2015-11-10
发明人： John H. Zhang , Yiheng Xu , Lawrence A. Clevenger , Carl Radens , Edem Wornyo
IPC分类号： H03H11/40 , H01L23/525 , H01L49/02 , H01F17/02 , H01L23/522 , H01F17/00
CPC分类号： H01L23/5256 , H01F17/0006 , H01F17/02 , H01F2017/0073 , H01L23/522 , H01L23/5227 , H01L23/5252 , H01L28/10 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.
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公开(公告)号：US09786551B2
公开(公告)日：2017-10-10
申请号：US14264803
申请日：2014-04-29
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/528 , H01L21/033 , H01L21/311 , H01L23/522
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/31144 , H01L23/5228 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a substrate with an interlevel dielectric layer positioned above the substrate. First trenches having a first depth are formed in the interlevel dielectric layer and a metal material fills the first trenches to form first interconnection lines. Second trenches having a second depth are also formed in the interlevel dielectric layer and filled with a metal material to form second interconnection lines. The first and second interconnection lines have a substantially equal pitch, which in a preferred implementation is a sub-lithographic pitch, and different resistivities due to the difference in trench depth. The first and second trenches are formed with an etching process through a hard mask having corresponding first and second openings of different depths. A sidewall image transfer process is used to define sub-lithographic structures for forming the first and second openings in the hard mask.
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公开(公告)号：US09659820B2
公开(公告)日：2017-05-23
申请号：US15143969
申请日：2016-05-02
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu , Richard Stephen Wise , Akil K. Sutton , Terry Allen Spooner , Nicole A. Saulnier
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/027 , H01L21/311
CPC分类号： H01L21/76897 , H01L21/0274 , H01L21/31116 , H01L21/31144 , H01L21/76808 , H01L21/7681 , H01L21/76816 , H01L21/7682 , H01L21/76835 , H01L21/76843 , H01L21/76877 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.
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公开(公告)号：US09658523B2
公开(公告)日：2017-05-23
申请号：US14231448
申请日：2014-03-31
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu , Richard Stephen Wise , Terry Spooner , Nicole A. Saulnier
IPC分类号： G03F1/36 , H01L21/768 , H01L23/522 , H01L23/528 , H01L21/027 , H01L21/311
CPC分类号： G03F1/36 , G03F1/00 , H01L21/0274 , H01L21/31144 , H01L21/76808 , H01L21/76816 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.
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公开(公告)号：US20160064326A1
公开(公告)日：2016-03-03
申请号：US14937812
申请日：2015-11-10
发明人： John H. Zhang , Yiheng Xu , Lawrence A. Clevenger , Carl Radens , Edem Wornyo
IPC分类号： H01L23/525 , H01L49/02 , H01L23/522
CPC分类号： H01L23/5256 , H01F17/0006 , H01F17/02 , H01F2017/0073 , H01L23/522 , H01L23/5227 , H01L23/5252 , H01L28/10 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.
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