公开(公告)号：US09747995B2

公开(公告)日：2017-08-29

申请号：US15176269

申请日：2016-06-08

申请人： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

发明人： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC分类号： G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

摘要： Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US08592912B2

公开(公告)日：2013-11-26

申请号：US13106481

申请日：2011-05-12

申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jae-Joo Shim

发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jae-Joo Shim

IPC分类号： H01L29/78

CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a plurality of conductive patterns stacked on a substrate and spaced apart from each other and a pad pattern including a flat portion extending in a first direction parallel to the substrate from one end of any one of the plurality of conductive patterns, and a landing sidewall portion extending upward from a top surface of the flat portion, wherein a width of a portion of the landing sidewall portion in a second direction parallel to the substrate and perpendicular to the first direction is less than a width of the flat portion.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括：多个导电图案，其堆叠在基板上并彼此间隔开;以及焊盘图案，其包括从多个导电图案中的任一个的一端平行于基板延伸的平坦部分， 以及从所述平坦部分的顶表面向上延伸的着陆侧壁部分，其中所述着陆侧壁部分在平行于所述基板并且垂直于所述第一方向的第二方向上的一部分的宽度小于所述平坦部分的宽度 。

公开(公告)号：US20100207184A1

公开(公告)日：2010-08-19

申请号：US12658154

申请日：2010-02-03

申请人： Kihyun Kim ,  Hansoo Kim ,  Wonseok Cho ,  Jinho Kim ,  Jaehoon Jang ,  Byoungkeun Son

发明人： Kihyun Kim ,  Hansoo Kim ,  Wonseok Cho ,  Jinho Kim ,  Jaehoon Jang ,  Byoungkeun Son

IPC分类号： H01L29/78

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556

摘要： A semiconductor device includes insulating patterns and gate patterns alternately stacked on a substrate; an active pattern on the substrate, which extends upward along sidewalls of the insulating patterns and the gate patterns; data storage patterns interposed between the gate patterns and the active pattern; and a source/drain region disposed in the active pattern between a pair of gate patterns adjacent to each other.

摘要翻译： 半导体器件包括交替层叠在衬底上的绝缘图案和栅极图案; 衬底上的有源图案，其沿绝缘图案和栅极图案的侧壁向上延伸; 插入在栅极图案和活动图案之间的数据存储图案; 以及设置在相互邻近的一对栅极图案之间的有源图案中的源极/漏极区域。

公开(公告)号：US08742466B2

公开(公告)日：2014-06-03

申请号：US12953748

申请日：2010-11-24

申请人： Jae-Joo Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Woojin Cho

发明人： Jae-Joo Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Woojin Cho

IPC分类号： H01L23/52

CPC分类号： H01L23/3157 ,  H01L21/76816 ,  H01L23/291 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

摘要翻译： 提供一种三维半导体器件及其制造方法。 三维半导体器件可以包括用于提供间隙区域的模具结构和包括设置在间隙区域中的多个互连图案的互连结构。 模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。

公开(公告)号：US08482138B2

公开(公告)日：2013-07-09

申请号：US13012485

申请日：2011-01-24

申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

IPC分类号： H01L29/40

CPC分类号： H01L21/768 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.

摘要翻译： 提供一种三维半导体器件及其制造方法。 该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。 第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。 第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。 这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。

公开(公告)号：US08394716B2

公开(公告)日：2013-03-12

申请号：US12963241

申请日：2010-12-08

申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

IPC分类号： H01L21/44

CPC分类号： H01L21/768 ,  H01L23/5226 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.

摘要翻译： 三维半导体器件可以包括在基板的布线和接触区域上包括布线和接触区域以及薄膜结构的基板。 薄膜结构可以包括在接触区域中限定梯形结构的多个交替布线层和层间绝缘层，使得每个布线层包括在接触区域中延伸超过其它布线层的接触表面 离衬底更远。 多个接触结构可以在垂直于衬底的表面的方向上延伸，其中每个接触结构电连接到相应的一个接线层的接触表面。 还讨论了相关方法。

公开(公告)号：US20110180941A1

公开(公告)日：2011-07-28

申请号：US13012485

申请日：2011-01-24

申请人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

发明人： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

IPC分类号： H01L23/52 ,  H01L21/28

CPC分类号： H01L21/768 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.

摘要翻译： 提供一种三维半导体器件及其制造方法。 该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。 第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。 第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。 这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。

公开(公告)号：US20110147801A1

公开(公告)日：2011-06-23

申请号：US12953748

申请日：2010-11-24

申请人： Jae-Joo SHIM ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Woojin Cho

发明人： Jae-Joo SHIM ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Woojin Cho

IPC分类号： H01L27/06

CPC分类号： H01L23/3157 ,  H01L21/76816 ,  H01L23/291 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

摘要翻译： 提供一种三维半导体器件及其制造方法。 三维半导体器件可以包括用于提供间隙区域的模具结构和包括布置在间隙区域中的多个互连图案的互连结构。 模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。

公开(公告)号：US09111799B2

公开(公告)日：2015-08-18

申请号：US13109230

申请日：2011-05-17

申请人： Sung-Min Hwang ,  Kyoung-Hoon Kim ,  Hansoo Kim ,  Jae-Joo Shim ,  Jaehoon Jang ,  Wonseok Cho ,  Byoungkeun Son ,  Hoosung Cho

发明人： Sung-Min Hwang ,  Kyoung-Hoon Kim ,  Hansoo Kim ,  Jae-Joo Shim ,  Jaehoon Jang ,  Wonseok Cho ,  Byoungkeun Son ,  Hoosung Cho

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate doped with a first conductive type dopant, a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction, and a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括掺杂有第一导电型掺杂剂的衬底，并且在衬底上并排布置并沿第一方向延伸的多个堆叠结构，每个堆叠结构包括彼此间隔开的栅电极， 堆叠结构，包括一对堆叠结构，其在垂直于第一方向的第二方向上以第一间隔彼此间隔开;以及拾取区域，在所述一对堆叠结构中的衬底中沿第一方向延伸并掺杂 第一导电型掺杂剂。

公开(公告)号：US20110291172A1

公开(公告)日：2011-12-01

申请号：US13109230

申请日：2011-05-17

申请人： Sung-Min Hwang ,  Kyoung-Hoon Kim ,  Hansoo Kim ,  Jae-Joo Shim ,  Jaehoon Jang ,  Wonseok Cho ,  Byoungkeun Son ,  Hoosung Cho

发明人： Sung-Min Hwang ,  Kyoung-Hoon Kim ,  Hansoo Kim ,  Jae-Joo Shim ,  Jaehoon Jang ,  Wonseok Cho ,  Byoungkeun Son ,  Hoosung Cho

IPC分类号： H01L29/78

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate doped with a first conductive type dopant, a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction, and a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括掺杂有第一导电型掺杂剂的衬底，并且在衬底上并排布置并沿第一方向延伸的多个堆叠结构，每个堆叠结构包括彼此间隔开的栅电极， 堆叠结构，包括一对堆叠结构，其在垂直于第一方向的第二方向上以第一间隔彼此间隔开;以及拾取区域，在所述一对堆叠结构中的衬底中沿第一方向延伸并掺杂 第一导电型掺杂剂。