公开(公告)号：US20090225598A1

公开(公告)日：2009-09-10

申请号：US12468723

申请日：2009-05-19

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C16/06 ,  G11C29/00 ,  G11C8/10

CPC classification number: G11C8/20 ,  G06F11/1068 ,  G11C8/10 ,  G11C29/808 ,  G11C2029/0411

Abstract: A method, apparatus and system are described which provide a memory device having an array of cells which may be selectively designated for either error correction code use or redundancy cell use.

Abstract translation: 描述了提供具有可以选择性地指定用于纠错码使用或冗余电池使用的单元阵列的存储器件的方法，装置和系统。

公开(公告)号：US20080192538A1

公开(公告)日：2008-08-14

申请号：US12107315

申请日：2008-04-22

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C16/34 ,  G11C16/06

CPC classification number: G11C7/18 ,  G11C7/02 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

Abstract: A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at boundaries between even and odd sections of the array to further reduce floating gate coupling.

Abstract translation: NAND存储器架构将页面的所有偶数位线布置在一起，并且将页面的所有奇数位线布置在一起，使得在相同字线上的相邻位线上执行编程操作以减少浮动栅极耦合。 可以在阵列的偶数和奇数部分之间的边界处使用非连接的位线，以进一步减少浮动栅极耦合。

公开(公告)号：US20080074933A1

公开(公告)日：2008-03-27

申请号：US11515629

申请日：2006-09-05

Applicant: Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

Inventor： Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

IPC: G11C7/10

CPC classification number: G11C7/1042 ,  G11C7/1051 ,  G11C16/26 ,  G11C2207/2245

Abstract: A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

Abstract translation: 描述了利用高速缓存读取操作模式的非易失性存储器，其中由读出放大器从存储器阵列读取/感测存储器的下一页，同时从存储器I / O缓冲器，其中下一页是用户选择的。 这种随机高速缓存读取模式允许具有随机页面读取功能的存储器，其中要读取的下一页数据的地址是用户可选择的，这受益于由于并发数据而导致的高速缓存读取操作模式的低等待时间 感测和数据I / O。

公开(公告)号：US07345924B2

公开(公告)日：2008-03-18

申请号：US11546171

申请日：2006-10-11

Applicant: Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

Inventor： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

IPC: G11C16/04

CPC classification number: G11C16/10

Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Abstract translation: 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。

公开(公告)号：US20070291565A1

公开(公告)日：2007-12-20

申请号：US11452697

申请日：2006-06-14

Applicant: Jin-Man Han

Inventor： Jin-Man Han

IPC: G11C7/02

CPC classification number: G11C7/18 ,  G11C7/02 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

Abstract: A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at boundaries between even and odd sections of the array to further reduce floating gate coupling.

Abstract translation: NAND存储器架构将页面的所有偶数位线布置在一起，并且将页面的所有奇数位线布置在一起，使得在相同字线上的相邻位线上执行编程操作以减少浮动栅极耦合。 可以在阵列的偶数和奇数部分之间的边界处使用非连接的位线，以进一步减少浮动栅极耦合。

公开(公告)号：US20070133294A1

公开(公告)日：2007-06-14

申请号：US11675151

申请日：2007-02-15

Applicant: Jin-Man Han ,  Benjamin Louie

Inventor： Jin-Man Han ,  Benjamin Louie

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C16/0483 ,  G11C16/3427

Abstract: The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than Vpass. The memory cells on this unselected wordline that are biased at this voltage block the gate induced drain leakage from the cells further up in the array. The remaining unselected wordlines are biased at Vpass. In another embodiment, a second source select gate line is added to the array. The source select gate line that is closest to the wordlines is biased at the voltage that is less than Vpass in order to block the gate induced drain leakage from the array.

Abstract translation: 用于减少闪速存储器阵列中的编程干扰的方法在编程电压下偏置所选择的字线。 未选择的字线之一，比所选择的字线更接近阵列地，被偏置在小于V 的电压。 在这个未被选择的字线上被偏置在该电压下的存储器单元阻挡栅极引起的漏极从阵列中的细胞进一步上升。 剩余的未选择的字线偏向V 。 在另一个实施例中，第二源选择栅极线被添加到阵列。 最靠近字线的源选择栅极线被偏置在小于V 的电压，以便阻挡来自阵列的栅感应漏极泄漏。

公开(公告)号：US20060245290A1

公开(公告)日：2006-11-02

申请号：US11116597

申请日：2005-04-28

Applicant: Jin-Man Han ,  Aaron Yip

Inventor： Jin-Man Han ,  Aaron Yip

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G06F12/0246 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3427 ,  G11C29/76 ,  G11C29/82 ,  Y02D10/13

Abstract: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.

公开(公告)号：US5784322A

公开(公告)日：1998-07-21

申请号：US772356

申请日：1996-12-23

Applicant: Jin-Man Han ,  Jei-Hwan Yoo

Inventor： Jin-Man Han ,  Jei-Hwan Yoo

IPC: G11C11/401 ,  G11C5/14 ,  G11C7/24 ,  G11C29/04 ,  G11C29/50 ,  G11C7/00

CPC classification number: G11C29/50 ,  G11C11/401 ,  G11C2029/5006

Abstract: A standby current detecting circuit for use in a semiconductor memory device and method thereof are described. The memory device has a plurality of memory cells arranged at crossing points of a plurality of word lines and a plurality of bit lines. A plurality of switches are associated with each memory cell. A current path supplies current to each memory cell through the switch associated with each memory cell. A plurality of decoders are provided with each decoder for detecting a standby current supplied on one such current path for the memory cell. Each decoder includes control logic for selectively opening and isolating the switch associated with the memory cell in a standby current detection mode.

Abstract translation: 描述了用于半导体存储器件的待机电流检测电路及其方法。 存储器件具有布置在多个字线和多个位线的交叉点处的多个存储器单元。 多个开关与每个存储单元相关联。 当前路径通过与每个存储器单元相关联的开关向每个存储器单元提供电流。 提供多个解码器，每个解码器用于检测在存储单元的一个这样的电流路径上提供的待机电流。 每个解码器包括用于在待机电流检测模式中选择性地打开和隔离与存储器单元相关联的开关的控制逻辑。

公开(公告)号：US5650977A

公开(公告)日：1997-07-22

申请号：US637425

申请日：1996-04-25

Applicant: Kye-Hyun Kyung ,  Jei-Hwan Yoo ,  Jin-Man Han

Inventor： Kye-Hyun Kyung ,  Jei-Hwan Yoo ,  Jin-Man Han

IPC: G11C11/41 ,  G11C5/02 ,  G11C5/06 ,  G11C8/12 ,  G11C11/401 ,  G11C8/00

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/12

Abstract: An integrated circuit memory device includes a plurality of memory cells, a plurality of data lines, a memory cell selector, and a memory cell connector. The memory cells are arranged in a matrix of rows and columns wherein the plurality of memory cells are further grouped in banks with each bank including at least two rows of memory cells. Each of the data lines extends along one of the columns of memory cells so that each of the data lines extends along memory cells from each of the banks of memory cells. The memory cell selector includes a row decoder which selects one of the plurality of rows, a column decoder which selects one of the plurality of columns, and a bank decoder which selects one of the banks. The connector connects one of the memory cells to a respective data line in response to the memory cell selector. Accordingly, data from only one of the memory cells is provided on a respective one of the data lines at any point and time.

Abstract translation: 集成电路存储器件包括多个存储单元，多条数据线，存储单元选择器和存储单元连接器。 存储器单元被布置成行和列的矩阵，其中多个存储器单元进一步分组为库，每个存储体包括至少两行存储单元。 每个数据线沿存储器单元的列之一延伸，使得每个数据线沿着存储器单元的每一组的存储器单元延伸。 存储单元选择器包括选择多个行之一的行解码器，选择多个列之一的列解码器和选择一个存储体的存储体解码器。 该连接器响应于存储单元选择器，将一个存储单元连接到相应的数据线。 因此，仅在一个存储单元中的数据在任何时间点都被提供在数据线的相应一个上。

公开(公告)号：US08379448B2

公开(公告)日：2013-02-19

申请号：US13308405

申请日：2011-11-30

Applicant: Jin-Man Han ,  Aaron Yip

Inventor： Jin-Man Han ,  Aaron Yip

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00

CPC classification number: G11C29/846 ,  G11C29/82 ,  G11C2216/30

Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.

Abstract translation: 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个列的存储块。 每个列包括位线和位线上的多个存储单元。 多个列包括多组常规列和多组冗余列。 该装置还包括多个数据锁存器。 每个数据锁存器被配置为存储从相应的一组常规列读取的数据。 该装置还包括多个冗余数据锁存器。 每个冗余数据锁存器被配置为存储从相应的一组冗余列读取的数据。 该装置还包括多路复用器，其被配置为选择性地从多个数据锁存器和多个冗余数据锁存器输出数据。