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93 条记录 (耗时 0.03 秒)

    Integration process to increase high voltage breakdown performance
    51.
    发明授权
    Integration process to increase high voltage breakdown performance 有权
    集成过程提高高压击穿性能

    公开(公告)号：US06348382B1

    公开(公告)日：2002-02-19

    申请号：US09392391

    申请日：1999-09-09

    申请人： Hung-Der Su ,  Chrong Jung Lin ,  Jong Chen ,  Wen-Ting Chu

    发明人： Hung-Der Su ,  Chrong Jung Lin ,  Jong Chen ,  Wen-Ting Chu

    IPC分类号： H01L218234

    CPC分类号： H01L21/823857 ,  H01L21/823814

    摘要： A new process is provided whereby LDD regions for HV CMOS devices and for LV CMOS devices are created using one processing sequence. The gate electrodes for both the High Voltage and the Low Voltage devices are created on the surface of a silicon substrate. The High Voltage LDD (HVLDD) is performed self-aligned with the HV CMOS gate electrode, a gate anneal is performed for both the HV and the LV CMOS devices. The Low Voltage LDD (LVLDD) is performed self-aligned with the LV CMOS gate electrodes. The gate electrodes of the CMOS devices are after this completed with the formation of the gate spacers, the source/drain implants and the back-end processing that is required for CMOS devices.

    摘要翻译： 提供了一种新的方法，由此使用一个处理顺序创建用于HV CMOS器件和LV CMOS器件的LDD区域。 用于高电压和低电压器件的栅电极都在硅衬底的表面上产生。 高压LDD（HVLDD）与HV CMOS栅电极自对准，对HV和LV CMOS器件进行栅极退火。 低压LDD（LVLDD）与LV CMOS栅电极自对准。 在CMOS器件的栅电极完成之后，形成栅极间隔物，源极/漏极注入和CMOS器件所需的后端处理。

    Tilt-angle ion implant to improve junction breakdown in flash memory application
    52.
    发明授权
    Tilt-angle ion implant to improve junction breakdown in flash memory application 有权
    倾斜离子注入，以改善闪存应用中的结点故障

    公开(公告)号：US06297098B1

    公开(公告)日：2001-10-02

    申请号：US09431236

    申请日：1999-11-01

    申请人： Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen ,  Wen-Ting Chu

    发明人： Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen ,  Wen-Ting Chu

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  H01L21/26586

    摘要： A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

    摘要翻译： 公开了一种用于在闪速存储器应用中用于非易失性存储器和DDD（双掺杂漏极）的高压器件中形成LDD（轻掺杂漏极）的方法。 高压器件通过以倾斜角度使用两个连续的离子注入形成，其提供了接合点附近的掺杂分布的改进的灰度级，并且在更高的电压下提高了结点击穿。 层叠闪存单元中的双掺杂漏极也通过两次注入形成，但是以最佳倾角形成，其中第一次注入被轻掺杂，而第二次重掺杂。 由此产生的DDD提供更快的编程速度，减少编程电流，增加读取电流和减少闪存单元中的漏极干扰。

    Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash
    53.
    发明授权
    Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash 有权
    通过堆叠栅极闪存中的横向耦合来增加字线与浮动栅极的耦合比的方法

    公开(公告)号：US6153494A

    公开(公告)日：2000-11-28

    申请号：US310257

    申请日：1999-05-12

    申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

    发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

    IPC分类号： H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/76

    CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

    摘要： A method is provided for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. This is accomplished by first depositing an unconventionally high or thick layer of nitride and then forming a shallow trench isolation (STI) through the nitride layer into the substrate, filling the STI with isolation oxide, removing the nitride thus leaving behind a deep opening about the filled STI, filling conformally the opening with a first polysilicon layer to form a floating gate, forming interpoly oxide layer over the floating gate, and then forming a second polysilicon layer to form the control gate and finally forming the self-aligned source of the stacked-gate flash memory cell of the invention. A stacked-gate flash memory cell is also provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.

    摘要翻译： 提供一种用于形成具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极快闪存储器单元的方法。 这是通过首先沉积非常规高或较厚的氮化物层，然后通过氮化物层形成浅沟槽隔离（STI）到衬底中，用隔离氧化物填充STI，从而除去氮化物，从而留下围绕 填充STI，用第一多晶硅层保形地填充开口以形成浮置栅极，在浮置栅极上形成多晶硅层，然后形成第二多晶硅层以形成控制栅极，并最终形成堆叠的自对准源 本发明的闪存单元。 还提供了堆叠栅极闪存单元，其具有具有高阶氧化物和高横向耦合的浅沟槽隔离。

    Stack gate flash memory cell featuring symmetric self aligned contact structures
    54.
    发明授权
    Stack gate flash memory cell featuring symmetric self aligned contact structures 有权
    具有对称自对准接触结构的堆栈门闪存单元

    公开(公告)号：US6037223A

    公开(公告)日：2000-03-14

    申请号：US177342

    申请日：1998-10-23

    申请人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Di-Son Kuo

    发明人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Di-Son Kuo

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/11521

    摘要： A process for fabricating a flash memory cell, featuring self-aligned contact structures, overlying and contacting, self-aligned source, and self-aligned drain regions, located between stack gate structures, has been developed. The stack gate structures, located on an underlying silicon dioxide, tunnel oxide layer, are comprised of: a capping insulator shape; a polysilicon control gate shape; an inter-polysilicon dielectric shape; and a polysilicon floating gate shape. The use of self-aligned contact structures, and self-aligned source regions, allows increased cell densities to be achieved.

    摘要翻译： 已经开发了一种用于制造闪存单元的方法，其特征在于位于堆叠栅极结构之间的自对准接触结构，覆盖和接触自对准源极和自对准漏极区。 位于下面的二氧化硅隧道氧化物层上的堆叠栅极结构包括：封盖绝缘体形状; 多晶硅控制门形状; 多晶硅间介质形状; 和多晶硅浮栅形状。 使用自对准接触结构和自对准的源区域可以实现提高的细胞密度。

    Process for forming self-aligned source in flash cell using SiN spacer as hard mask
    55.
    发明授权
    Process for forming self-aligned source in flash cell using SiN spacer as hard mask 有权
    使用SiN间隔物作为硬掩模在闪存单元中形成自对准源的工艺

    公开(公告)号：US6001687A

    公开(公告)日：1999-12-14

    申请号：US283849

    申请日：1999-04-01

    申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

    发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Chrong-Jung Lin ,  Hung-Der Su ,  Jong Chen

    IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/8239

    CPC分类号： H01L27/11521

    摘要： When FLASH cells are made in association with STI (as opposed to LOCOS) it is often the case that stringers of silicon nitride are left behind after the spacers have been formed. This problem has been eliminated by requiring that the oxide in the STI trenches remain in place at the time that the silicon nitride spacers are formed. After that, the oxide is removed in the usual manner, following which a SALICIDE process is used to form a self aligned source line. When this sequence is followed no stringers are left behind on the walls of the trench, guaranteeing the absence of any open circuits or high resistance regions in the source line.

    摘要翻译： 当与STI（与LOCOS相反）制成FLASH单元时，通常在形成间隔物之后留下氮化硅桁条。 通过要求在形成氮化硅间隔物的时刻STI槽中的氧化物保持在适当位置，已经消除了这个问题。 之后，以通常的方式去除氧化物，随后使用SALICIDE工艺来形成自对准的源极线。 当遵循该顺序时，沟槽的壁上不留下桁条，保证在源极线中不存在任何开路或高电阻区域。

    SEMICONDUCTOR COMPOSITE FILM WITH HETEROJUNCTION AND MANUFACTURING METHOD THEREOF
    58.
    发明申请
    SEMICONDUCTOR COMPOSITE FILM WITH HETEROJUNCTION AND MANUFACTURING METHOD THEREOF 有权
    具有异质性的半导体复合膜及其制造方法

    公开(公告)号：US20140159111A1

    公开(公告)日：2014-06-12

    申请号：US14048971

    申请日：2013-10-08

    申请人： Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang

    发明人： Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang

    IPC分类号： H01L21/02 ,  H01L29/12

    CPC分类号： H01L29/205 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/02664 ,  H01L21/30612 ,  H01L29/12 ,  H01L29/2003 ,  H01L29/7845 ,  H01L29/7849

    摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.

    摘要翻译： 本发明公开了一种具有异质结的半导体复合膜及其制造方法。 半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步 包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。 该凹槽用于减轻半导体复合膜中的应变。