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    Profile engineered thin film devices and structures
    51.
    发明授权
    Profile engineered thin film devices and structures 有权
    型材设计薄膜器件和结构

    公开(公告)号：US08822301B2

    公开(公告)日：2014-09-02

    申请号：US13791721

    申请日：2013-03-08

    申请人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    发明人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    IPC分类号： H01L21/20

    CPC分类号： H01L21/36 ,  C23C18/08 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1295 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76871 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L28/40 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/6675 ,  H01L29/7881 ,  H01L29/872 ,  H05K1/16 ,  H05K1/162 ,  H05K3/125 ,  H05K2201/098

    摘要： The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

    摘要翻译： 本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法 通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。 平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。 本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。 这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。 均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

    Method characterizing materials for a trench isolation structure having low trench parasitic capacitance
    53.
    发明授权
    Method characterizing materials for a trench isolation structure having low trench parasitic capacitance 有权
    用于具有低沟槽寄生电容的沟槽隔离结构的方法表征材料

    公开(公告)号：US08021955B1

    公开(公告)日：2011-09-20

    申请号：US12574426

    申请日：2009-10-06

    申请人： Venkatesh P. Gopinath ,  Arvind Kamath ,  Mohammad R. Mirabedini ,  Ming-Yi Lee

    发明人： Venkatesh P. Gopinath ,  Arvind Kamath ,  Mohammad R. Mirabedini ,  Ming-Yi Lee

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224

    摘要： Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.

    摘要翻译： 提供了用于在集成电路基板上形成多层隔离结构的方法和组合物。 工艺可以包括为下电介质层选择下电介质材料，并选择用于上电介质层的上电介质材料。 选择对应于下部和上部介电材料的厚度的一系列有效介电常数。 下介电层和上电介质层中的每一个的厚度范围由可接受的介电常数的范围决定，使用表示与下部上部电介质层的材料的厚度对应的有效介电常数的信息，能够形成多层电介质层， 层隔离结构。

    METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT
    54.
    发明授权
    METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN SOME TRANSISTORS OF A HYBRID INTEGRATED CIRCUIT TO OBTAIN INCREASED DIFFERENTIAL IN GATE INSULATOR THICKNESS WITH OTHER TRANSISTORS OF THE HYBRID CIRCUIT 有权
    在混合集成电路的某些晶体管中减少硅氧烷栅绝缘体厚度的方法，以获得具有混合电路的其他晶体管的栅绝缘体厚度增加的差异

    公开(公告)号：US06521549B1

    公开(公告)日：2003-02-18

    申请号：US09724225

    申请日：2000-11-28

    申请人： Arvind Kamath ,  Rajiv Patel ,  Ravindra M. Kapre

    发明人： Arvind Kamath ,  Rajiv Patel ,  Ravindra M. Kapre

    IPC分类号： H01L21469

    CPC分类号： H01L21/823462

    摘要： A relatively thin gate insulator of a digital switching transistor is formed from a layer of silicon oxynitride which was initially formed by implanting nitrogen atoms in a silicon substrate and oxidizing the nitrogen and silicon. It has been discovered that an outer layer of silicon dioxide is formed as a part of the silicon oxynitride layer. Removing this outer layer of silicon dioxide from the silicon oxynitride layer leaves a thin remaining layer of substantially-only silicon oxynitride as the gate insulator. Thinner gate insulators of approximately 15-21 angstroms, for example, can be formed from a grown thickness of 60 angstroms, for example. Gate insulators for digital and analog transistors may be formed simultaneously with a greater differential in thickness been possible by using conventional nitrogen implantation techniques.

    摘要翻译： 数字开关晶体管的相对薄的栅极绝缘体由氮氧化硅层形成，其最初通过在硅衬底中注入氮原子并氧化氮和硅而形成。 已经发现，作为氧氮化硅层的一部分形成二氧化硅的外层。 从氮氧化硅层中除去二氧化硅外层留下基本上只有氮氧化硅的薄剩余层作为栅极绝缘体。 例如，大约15-21埃的较薄的栅极绝缘体可以由例如60埃的生长厚度形成。 用于数字和模拟晶体管的栅极绝缘体可以同时形成，通过使用常规氮注入技术，可以获得更大的厚度差。

    Diffusion Barrier Coated Substrates and Methods of Making the Same
    55.
    发明申请
    Diffusion Barrier Coated Substrates and Methods of Making the Same 有权
    扩散屏蔽涂层基板及其制作方法

    公开(公告)号：US20110017997A1

    公开(公告)日：2011-01-27

    申请号：US12790627

    申请日：2010-05-28

    申请人： Arvind Kamath ,  Michael Kocsis ,  Kevin McCarthy ,  Gloria Man Ting Wong

    发明人： Arvind Kamath ,  Michael Kocsis ,  Kevin McCarthy ,  Gloria Man Ting Wong

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L29/78603 ,  H01L27/1218 ,  H01L29/78681 ,  H01L29/7869

    摘要： Semiconductor devices on a diffusion barrier coated metal substrates, and methods of making the same are disclosed. The semiconductor devices include a metal substrate, a diffusion barrier layer on the metal substrate, an insulator layer on the diffusion barrier layer, and a semiconductor layer on the insulator layer. The method includes forming a diffusion barrier layer on the metal substrate, forming an insulator layer on the diffusion barrier layer; and forming a semiconductor layer on the insulator layer. Such diffusion barrier coated substrates prevent diffusion of metal atoms from the metal substrate into a semiconductor device formed thereon.

    摘要翻译： 公开了扩散阻挡涂层金属基板上的半导体器件及其制造方法。 半导体器件包括金属衬底，金属衬底上的扩散阻挡层，扩散阻挡层上的绝缘体层以及绝缘体层上的半导体层。 该方法包括在金属基板上形成扩散阻挡层，在扩散阻挡层上形成绝缘体层; 以及在所述绝缘体层上形成半导体层。 这种扩散阻挡涂层的基板防止金属原子从金属基板扩散到形成在其上的半导体器件中。

    Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance
    57.
    发明授权
    Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance 有权
    制造具有低沟槽寄生电容的浅沟槽隔离结构的方法

    公开(公告)号：US07001823B1

    公开(公告)日：2006-02-21

    申请号：US09991202

    申请日：2001-11-14

    申请人： Venkatesh P. Gopinath ,  Arvind Kamath ,  Mohammad R. Mirabedini ,  Ming-Yi Lee

    发明人： Venkatesh P. Gopinath ,  Arvind Kamath ,  Mohammad R. Mirabedini ,  Ming-Yi Lee

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224

    摘要： Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.

    摘要翻译： 提供了用于在集成电路基板上形成隔离结构的方法和组合物。 首先，在集成电路基板中蚀刻沟槽。 然后在沟槽中形成下介电层，使得下电介质层至少部分地填充沟槽。 然后在下介电层上形成上电介质层以产生隔离结构，上电介质层和下电介质层一起具有小于二氧化硅的有效介电常数，从而实现与隔离结构相关联的电容 要减少

    Method of shallow trench isolation formation and planarization
    58.
    发明授权
    Method of shallow trench isolation formation and planarization 失效
    浅沟槽隔离形成和平坦化的方法

    公开(公告)号：US06949446B1

    公开(公告)日：2005-09-27

    申请号：US10457942

    申请日：2003-06-09

    申请人： Arvind Kamath ,  Venkatesh P. Gopinth

    发明人： Arvind Kamath ,  Venkatesh P. Gopinth

    IPC分类号： H01L21/302 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/31055 ,  H01L21/76229

    摘要： Provided is a technique for fabrication of STIs in a semiconductor device using implantation of damaging high-energy ions to insulating material overburden to generally and/or selectively increase insulation overburden removal rates. This technique avoids the use of chemical mechanical planarization (CMP) with a combination of implantation and, in some instances, low cost batch etching. The electrical characteristics of devices created with the new technique match closely to those fabricated with the standard CMP-based technique.

    摘要翻译： 提供了一种用于在半导体器件中制造STI的技术，其使用损坏的高能离子将绝缘材料覆盖层绝缘覆盖层和/或选择性地提高绝缘覆盖层去除率。 这种技术避免了使用化学机械平面化（CMP）与组合注入，在某些情况下，低成本批量蚀刻。 使用新技术创建的器件的电气特性与使用标准CMP技术制造的器件的电气特性相匹配。

    Polysilicon gate salicidation
    60.
    发明授权
    Polysilicon gate salicidation 有权
    多晶硅栅盐化

    公开(公告)号：US06544829B1

    公开(公告)日：2003-04-08

    申请号：US10251016

    申请日：2002-09-20

    申请人： Venkatesh Gopinath ,  Mohammad Mirabedini ,  Charles E. May ,  Arvind Kamath

    发明人： Venkatesh Gopinath ,  Mohammad Mirabedini ,  Charles E. May ,  Arvind Kamath

    IPC分类号： H01L218238

    CPC分类号： H01L21/823835 ,  H01L21/823814 ,  H01L21/823878

    摘要： A method of fabricating a substantially completely silicided polysilicon gate electrode in a CMOS process flow. A hard mask material is formed on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon layer that overlies a gate oxide layer, and a well region disposed between isolation structures. Portions of the hard mask material are removed to define gate electrode masks that overlie first portions of the unpatterned polysilicon layer and the gate oxide layer, leaving exposed second portions of the unpatterned polysilicon layer and the gate oxide layer. The integrated circuit substrate is exposed to a dopant that passes through the second portions of the gate oxide layer but does not penetrate the first portions of the gate oxide layer that underlie the gate electrode masks, which defines source drain regions in the well region. The exposed second portions of the unpatterned polysilicon layer are removed to define polysilicon gate electrode precursors under the gate electrode masks. The gate electrode masks are removed from the polysilicon gate electrode precursors, and a metal layer is deposited over the polysilicon gate electrode precursors and the source drain regions. The integrated circuit substrate is annealed to substantially completely consume the polysilicon gate electrode precursors and form silicide gate electrodes from the polysilicon gate electrode precursors and the overlying metal layer, by which silicide contacts in the source drain regions are also formed.

    摘要翻译： 一种在CMOS工艺流程中制造基本上完全硅化的多晶硅栅电极的方法。 在集成电路基板上形成硬掩模材料，其中集成电路基板包括覆盖在栅极氧化物层上的未图案化的多晶硅层和设置在隔离结构之间的阱区域。 去除硬掩模材料的部分以限定覆盖未图案化多晶硅层和栅极氧化物层的第一部分的栅电极掩模，留下未图案化的多晶硅层和栅极氧化物层的暴露的第二部分。 集成电路基板暴露于穿过栅极氧化物层的第二部分但不穿过限定阱区中的源极漏极区域的栅极电极掩模之下的栅极氧化物层的第一部分的掺杂剂。 去除未图案化的多晶硅层的暴露的第二部分以在栅极电极掩模下限定多晶硅栅电极前体。 栅极电极掩模从多晶硅栅电极前驱体去除，并且金属层沉积在多晶硅栅极电极前体和源极漏极区上。 将集成电路基板退火以基本上完​​全消耗多晶硅栅极电极前体，并从多晶硅栅极电极前体和上覆金属层形成硅化物栅极电极，由此源极漏极区域中的硅化物接触也形成。