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51.发明授权Hybrid orientation substrate compatible deep trench capacitor embedded DRAM 失效混合取向衬底兼容深沟槽电容器嵌入式DRAM公开(公告)号：US07713814B2
公开(公告)日：2010-05-11
申请号：US11969502
申请日：2008-01-04
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L21/823807 , H01L21/84 , H01L27/0629 , H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/10897 , H01L27/1203
摘要： Method of limiting the lateral extent of a trench capacitor by a dielectric spacer in a hybrid orientations substrate is provided. The dielectric spacer separates a top semiconductor portion from an epitaxially regrown portion, which have different crystallographic orientations. The deep trench is formed as a substantially straight trench within the epitaxially regrown portion such that part of the epitaxially regrown portion remains overlying the dielectric spacer. The substantially straight trench is then laterally expanded to form a bottle shaped trench and to provide increased capacitance. The lateral expansion of the deep trench is self-limited by the dielectric spacer above the interface between the handle substrate and the buried insulator layer. During subsequent formation of a doped buried plate, the dielectric spacer blocks diffusion of dopants into the top semiconductor portion, providing a compact bottle shaped trench capacitor having high capacitance without introducing dopants into the top semiconductor portion.
摘要翻译： 提供了通过混合取向衬底中的电介质间隔物限制沟槽电容器的横向范围的方法。 电介质隔离物将顶部半导体部分与具有不同晶体取向的外延再生长部分分开。 深沟槽在外延再生长部分中形成为基本上直的沟槽，使得外延再生长部分的一部分保持覆盖在电介质间隔物上。 然后将基本上直的沟槽横向膨胀以形成瓶形沟槽并提供增加的电容。 深沟槽的横向膨胀由手柄衬底和掩埋绝缘体层之间的界面上方的电介质隔离板自限制。 在随后形成掺杂掩埋板期间，介电间隔物阻止掺杂剂扩散到顶部半导体部分中，提供具有高电容的紧凑的瓶形沟槽电容器，而不将掺杂剂引入顶部半导体部分。
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52.发明申请HYBRID ORIENTATION SUBSTRATE COMPATIBLE DEEP TRENCH CAPACITOR EMBEDDED DRAM 失效混合定向衬底兼容深度电容电容器嵌入式DRAM公开(公告)号：US20090176347A1
公开(公告)日：2009-07-09
申请号：US11969502
申请日：2008-01-04
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L21/823807 , H01L21/84 , H01L27/0629 , H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/10897 , H01L27/1203
摘要： Method of limiting the lateral extent of a trench capacitor by a dielectric spacer in a hybrid orientations substrate is provided. The dielectric spacer separates a top semiconductor portion from an epitaxially regrown portion, which have different crystallographic orientations. The deep trench is formed as a substantially straight trench within the epitaxially regrown portion such that part of the epitaxially regrown portion remains overlying the dielectric spacer. The substantially straight trench is then laterally expanded to form a bottle shaped trench and to provide increased capacitance. The lateral expansion of the deep trench is self-limited by the dielectric spacer above the interface between the handle substrate and the buried insulator layer. During subsequent formation of a doped buried plate, the dielectric spacer blocks diffusion of dopants into the top semiconductor portion, providing a compact bottle shaped trench capacitor having high capacitance without introducing dopants into the top semiconductor portion.
摘要翻译： 提供了通过混合取向衬底中的电介质间隔物限制沟槽电容器的横向范围的方法。 电介质隔离物将顶部半导体部分与具有不同晶体取向的外延再生长部分分开。 深沟槽在外延再生长部分中形成为基本上直的沟槽，使得外延再生长部分的一部分保持覆盖在电介质间隔物上。 然后将基本上直的沟槽横向膨胀以形成瓶形沟槽并提供增加的电容。 深沟槽的横向膨胀由手柄衬底和掩埋绝缘体层之间的界面上方的电介质隔离板自限制。 在随后形成掺杂掩埋板期间，介电间隔物阻止掺杂剂扩散到顶部半导体部分中，提供具有高电容的紧凑的瓶形沟槽电容器，而不将掺杂剂引入顶部半导体部分。
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53.发明授权Methods and structures for protecting one area while processing another area on a chip 失效在处理芯片上的另一个区域时保护一个区域的方法和结构公开(公告)号：US07497959B2
公开(公告)日：2009-03-03
申请号：US10709514
申请日：2004-05-11
申请人： Deok-kee Kim , Kenneth T. Settlemyer, Jr. , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth T. Settlemyer, Jr. , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
摘要翻译： 增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。 提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。 这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。
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公开(公告)号：US20090047756A1
公开(公告)日：2009-02-19
申请号：US12254960
申请日：2008-10-21
IPC分类号： H01L21/84 , H01L21/8242
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。
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公开(公告)号：US07459743B2
公开(公告)日：2008-12-02
申请号：US11161962
申请日：2005-08-24
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。
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公开(公告)号：US07439568B2
公开(公告)日：2008-10-21
申请号：US10906238
申请日：2005-02-10
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译： 提供了垂直场效应晶体管（“FET”），其包括晶体管本体区域和设置在与沟槽的侧壁相邻的衬底的绝缘体上的单晶半导体（“SOI”）区域中的源极和漏极区域。 衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。 掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。
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公开(公告)号：US07375413B2
公开(公告)日：2008-05-20
申请号：US11420527
申请日：2006-05-26
IPC分类号： H01L29/00
CPC分类号： H01L29/945 , H01L29/66181
摘要： A semiconductor fabrication method comprises steps of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. The method further comprises the steps of removing portions of the blocking layer on the {110} side wall surfaces without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.
摘要翻译： 半导体制造方法包括提供半导体结构的步骤。 半导体结构包括半导体衬底，半导体衬底中的沟槽。 沟槽包括侧壁，其包括{100}侧壁表面和{110}侧壁表面。 半导体结构还包括在{100}侧壁表面和{110}侧壁表面上的阻挡层。 该方法还包括以下步骤：除去{110}侧壁表面上的阻挡层的部分，而不去除{100}侧壁表面上的阻挡层的部分，使得{110}侧壁表面暴露于周围 周围。
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公开(公告)号：US07358586B2
公开(公告)日：2008-04-15
申请号：US10951745
申请日：2004-09-28
CPC分类号： H01L29/66772 , H01L21/304 , H01L21/30625 , H01L21/3065 , H01L21/76254 , H01L21/76275 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A bonded SOI wafer and a method for forming a bonded SOI wafer are provided. According to the disclosed method, a first semiconductor wafer is provided, having a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches extending from the outer surface inwardly into the semiconductor. The outer surface of the first wafer is bonded to the outer surface of a second semiconductor wafer to form a bonded wafer having a bulk semiconductor region, a buried dielectric layer overlying the bulk semiconductor region, and a semiconductor-on-insulator layer overlying the buried dielectric layer, with the dielectric filled trenches extending upwardly from the buried dielectric layer into the semiconductor-on-insulator layer. The thickness of the semiconductor-on-insulator layer is then reduced until uppermost surfaces of at least some of the dielectric filled trenches are at least partially exposed.
摘要翻译： 提供键合SOI晶片和形成键合SOI晶片的方法。 根据所公开的方法，提供第一半导体晶片，其具有设置在第一晶片的外表面处的第一介电层和从外表面向内延伸到半导体中的多个电介质填充沟槽。 第一晶片的外表面被接合到第二半导体晶片的外表面，以形成具有体半导体区域，覆盖体半导体区域的掩埋电介质层和覆盖在掩埋层上的绝缘体上半导体层的键合晶片 电介质层，其中介电填充的沟槽从掩埋介电层向上延伸到绝缘体上半导体层中。 然后减小绝缘体上半导体层的厚度，直到至少一些电介质填充沟槽的最上表面至少部分露出。
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59.发明申请公开(公告)号：US20080050873A1
公开(公告)日：2008-02-28
申请号：US11928135
申请日：2007-10-30
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/0218 , H01L27/10841 , H01L27/10864 , H01L27/10891
摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.
摘要翻译： 一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括构建在绝缘体上半导体（SOI）晶片上的多个垂直存储器单元和电耦合SOI的半导体本体和半导体衬底的主体接触 晶圆。 半导体本体包括用于垂直存储单元之一的存取装置的通道区域。 延伸穿过SOI晶片的掩埋介电层的主体接触件提供电流泄漏路径，其减少浮体对垂直存储单元的影响。 可以通过蚀刻延伸穿过SOI晶片的半导体主体和埋入介质层的通孔来形成本体接触，并且延伸到衬底中并且用导电材料部分地填充通孔，所述导电材料使半导体本体与衬底电耦合。
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公开(公告)号：US07264982B2
公开(公告)日：2007-09-04
申请号：US10904255
申请日：2004-11-01
IPC分类号： H01L21/027
CPC分类号： H01L31/105 , H01L31/03529 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： Trench type PIN photodetectors are formed by etching two sets of trenches simultaneously in a semiconductor substrate, the wide trenches having a width more than twice as great as the narrow trenches by a process margin; conformally filling both types of trenches with a sacrificial material doped with a first dopant and having a first thickness slightly greater than one half the width of the narrow trenches, so that the wide trenches have a remaining central aperture; stripping the sacrificial material from the wide trenches in an etch that removes a first thickness, thereby emptying the wide trenches; a) filling the wide trenches with a second sacrificial material of opposite polarity; or b) doping the wide trenches from the ambient such as by gas phase doping, plasma doping, ion implantation, liquid phase doping, infusion doping and plasma immersion ion implantation; diffusing the dopants into the substrate, forming p and n regions of the PIN diode; removing the first and the second sacrificial materials, and filling both the wide and the narrow sets of trenches with the same conductive material in contact with the diffused p and n regions.
摘要翻译： 通过在半导体衬底中同时蚀刻两组沟槽形成沟槽型PIN光电检测器，宽沟槽的宽度是窄沟槽的两倍以上的加工余量; 用掺杂有第一掺杂剂的牺牲材料保形地填充两种类型的沟槽，并且具有略大于窄沟槽宽度的一半的第一厚度，使得宽沟槽具有剩余的中心孔径; 在去除第一厚度的蚀刻中从宽的沟槽剥离牺牲材料，从而排空宽的沟槽; a）用相反极性的第二牺牲材料填充宽的沟槽; 或b）通过气相掺杂，等离子体掺杂，离子注入，液相掺杂，浸渍掺杂和等离子体浸入离子注入等方式，从环境中掺杂宽沟槽; 将掺杂剂扩散到衬底中，形成PIN二极管的p区和n区; 去除第一和第二牺牲材料，并用与扩散的p和n区域接触的相同导电材料填充宽和窄的沟槽组。
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