Semiconductor memory having multiple level storage structure
    51.
    发明授权
    Semiconductor memory having multiple level storage structure 失效
    具有多级存储结构的半导体存储器

    公开(公告)号:US4661929A

    公开(公告)日:1987-04-28

    申请号:US686018

    申请日:1984-12-24

    摘要: In a semiconductor memory includes a memory array consisting of a plurality of memory cells respectively having at least one storage capacitor, an addressing circuit which designates location of each memory cell, data lines which transmit data connected to said memory cells and data writing and reading circuits connected to said data lines. The semiconductor memory has a multiple level storage structure. In particular, the memory includes an arrangement for sequentially applying, on a time series basis, different voltages of at least 3 levels or more to the gate of a switching MOS transistor of said memory cells, a bias charge supplying means as said data reading circuit and a column register providing at least two or more storage cells which temporarily store said data.

    摘要翻译: 在半导体存储器中,包括由分别具有至少一个存储电容器的多个存储器单元组成的存储器阵列,指定每个存储单元的位置的寻址电路,发送连接到所述存储单元的数据的数据线和数据写入和读取电路 连接到所述数据线。 半导体存储器具有多级存储结构。 具体而言,该存储器包括用于按时间序列依次将至少3级以上的不同电压施加到所述存储单元的开关型MOS晶体管的栅极的装置,作为所述数据读取电路的偏置电荷供给装置 以及提供临时存储所述数据的至少两个或更多个存储单元的列寄存器。

    Low noise semiconductor memory
    55.
    发明授权
    Low noise semiconductor memory 失效
    低噪声半导体存储器

    公开(公告)号:US4958325A

    公开(公告)日:1990-09-18

    申请号:US238375

    申请日:1988-08-31

    IPC分类号: G11C7/18 G11C11/4097

    CPC分类号: G11C7/18 G11C11/4097

    摘要: A highly integrated semiconductor memory, particularly, a low noise dynamic memory. As the density of integration of the dynamic memory increases, the distance between data lines decreases and a new type of noise, which has hitherto been thought little of, displays itself. To cope with this problem in the semiconductor memory comprising a plurality of pairs of data lines arranged in substantially parallel relationship with each other, respective pairs having substantially the same electric characteristics, connection means provided in association with the respective data line pairs, a plurality of word lines laid to extend perpendicularly to the data line pairs, at least one memory cell connected to at least one of intersections of the word lines with data lines of the pairs, and a plurality of sense amplifier means respectively connected to the data line pairs to differentially detect signal voltages appearing on each data line pair, the plural data line pairs have an alternate arrangement of a pair of data lines transposed at an even number of places and a pair of data lines transposed at an odd number of places, and the sense amplifier means is operative to change voltage on one of the data lines of a pair to a high-level voltage and voltage on the other of the data lines of the pair of a low-level voltage.

    摘要翻译: 高度集成的半导体存储器,特别是低噪声动态存储器。 随着动态存储器的集成密度增加,数据线之间的距离减小,而迄今为止被认为很少的新型噪声显示出来。 为了在包括彼此基本上平行关系的多对数据线的半导体存储器中应对这个问题,具有基本上相同电特性的各对具有与各个数据线对相关联地设置的连接装置, 与数据线对垂直延伸的字线,至少一个存储单元连接到字线与该对的数据线的交点中的至少一个,以及分别连接到数据线对的多个读出放大器装置 差分检测每个数据线对上出现的信号电压,多个数据线对具有在偶数个位置处置换的一对数据线和在奇数个位置处置换的一对数据线的交替排列,并且感测 放大器装置可操作以将一对数据线之一上的电压改变为ot上的高电平电压和电压 她的数据线是一对低电平的电压。

    Memory module including module data wirings available as a memory access data bus
    56.
    发明授权
    Memory module including module data wirings available as a memory access data bus 有权
    存储器模块包括可用作存储器访问数据总线的模块数据配线

    公开(公告)号:US06628538B2

    公开(公告)日:2003-09-30

    申请号:US10105249

    申请日:2002-03-26

    IPC分类号: G11C506

    摘要: A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each individual memory modules are connected in serial form, and each individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.

    摘要翻译: 模块基板具有与多个存储器芯片中的各个芯片数据端子相关联地分别设置的多个模块数据端子对以及分别连接在多个模块数据端子对之间的多个模块数据布线。 多个模块数据布线连接到它们对应的芯片数据终端,并被配置为可用作存储器访问数据总线。 在并行布置多个存储器模块的存储器系统中,各个存储器模块的模块数据布线以串行形式连接,并且每个单独的模块数据布线不构成相对于主板上的数据总线的分支布线 的内存系统。 在存储器模块中,确保与存储器访问数据总线的宽度相对应的位数的并行访问。

    Semiconductor memory device
    57.
    发明授权

    公开(公告)号:US06563755B2

    公开(公告)日:2003-05-13

    申请号:US09986082

    申请日:2001-11-07

    IPC分类号: G11C700

    CPC分类号: G11C11/406

    摘要: A semiconductor memory device realizing a reduced cycle time while improving the ease of use is to be provided. Where a memory cell requires a periodic refresh action to hold stored information, a time multiplexing mode of performing, when a first memory operation on any memory cell to read or write stored information or information to be stored and a second memory operation, having a different address designation from the first memory operation, or a refresh operation compete for the same time segment, the second memory operation before or after such first memory operation, wherein the minimum access time needed for the first memory operation and the second memory operation or the refresh operation performed before or after the first memory operation is set shorter than the sum of the length of time required for the first memory operation and that required for the second memory operation or the refresh operation on condition that sets of information stored in the memory cells are not mutually affected in the first memory operation and the second memory operation or the refresh operation.

    Semiconductor memory device
    59.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号:US4942556A

    公开(公告)日:1990-07-17

    申请号:US377181

    申请日:1989-07-10

    IPC分类号: G11C15/04 G11C29/00 G11C29/44

    摘要: In a defect relieving technology which replaces defective memory cells of a semiconductor memory device by spare memory cells, use is made of an associative memory. Address information of a defective memory cell is stored as a reference data of the associative memory, and new address information of a spare memory cell is written down as output data of the associative memory. A variety of improvements are made to the associative memory. For instance, a plurality of coincidence detection signal lines of the associative memory are divided into at least two groups, and one group among them is selected by switching means. Reference data of the associative memory comprises three values consisting of binary information of "0" and "1", and don't care value "X". The associative memory further includes a plurality of electrically programable non-volatile semiconductor memory elements.

    摘要翻译: 在通过备用存储器单元代替半导体存储器件的缺陷存储单元的缺陷解除技术中,使用关联存储器。 存储有缺陷的存储单元的地址信息被存储为关联存储器的参考数据,并且备用存储单元的新地址信息被写入作为关联存储器的输出数据。 对联想记忆进行了各种改进。 例如,关联存储器的多个符合检测信号线被划分为至少两组,其中一组由切换装置选择。 关联存储器的参考数据包括由“0”和“1”的二进制信息组成的三个值,并且不关心值“X”。 关联存储器还包括多个可电可编程的非易失性半导体存储器元件。