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    Semiconductor memory having multiple level storage structure
    1.
    发明授权
    Semiconductor memory having multiple level storage structure 失效
    具有多级存储结构的半导体存储器

    公开(公告)号：US4661929A

    公开(公告)日：1987-04-28

    申请号：US686018

    申请日：1984-12-24

    申请人： Masakazu Aoki ,  Yoshinobu Nakagome ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    发明人： Masakazu Aoki ,  Yoshinobu Nakagome ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    IPC分类号： G06F11/10 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/56 ,  G11C11/40

    CPC分类号： G11C11/565 ,  G11C11/4091 ,  G11C7/065 ,  G06F11/1072 ,  G11C29/00 ,  G11C7/06

    摘要： In a semiconductor memory includes a memory array consisting of a plurality of memory cells respectively having at least one storage capacitor, an addressing circuit which designates location of each memory cell, data lines which transmit data connected to said memory cells and data writing and reading circuits connected to said data lines. The semiconductor memory has a multiple level storage structure. In particular, the memory includes an arrangement for sequentially applying, on a time series basis, different voltages of at least 3 levels or more to the gate of a switching MOS transistor of said memory cells, a bias charge supplying means as said data reading circuit and a column register providing at least two or more storage cells which temporarily store said data.

    摘要翻译： 在半导体存储器中，包括由分别具有至少一个存储电容器的多个存储器单元组成的存储器阵列，指定每个存储单元的位置的寻址电路，发送连接到所述存储单元的数据的数据线和数据写入和读取电路 连接到所述数据线。 半导体存储器具有多级存储结构。 具体而言，该存储器包括用于按时间序列依次将至少3级以上的不同电压施加到所述存储单元的开关型MOS晶体管的栅极的装置，作为所述数据读取电路的偏置电荷供给装置 以及提供临时存储所述数据的至少两个或更多个存储单元的列寄存器。

    Semiconductor memory having error correcting means
    2.
    发明授权
    Semiconductor memory having error correcting means 失效
    具有误差校正装置的半导体存储器

    公开(公告)号：US4726021A

    公开(公告)日：1988-02-16

    申请号：US853230

    申请日：1986-04-17

    申请人： Masashi Horiguchi ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    发明人： Masashi Horiguchi ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    IPC分类号： G06F11/10 ,  G11C29/24 ,  G01R31/28

    CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C29/24

    摘要： A semiconductor memory having an error correcting function is provided, which has a device by which the user finds no difficulty in making use of the semiconductor memory and can test it with ease. In the semiconductor memory, a signal indicative of the completion of the preparation for reading/writing is outputted from the memory so that the user, after detecting the output of this signal, performs reading/writing data. To facilitate tests, such as a memory cell test for a redundant bit (check bit), an encoding circuit test and a decoding circuit test, the present invention provides that the arranged tests can be made independently of each other.

    摘要翻译： 提供了具有纠错功能的半导体存储器，其具有用户不用利用半导体存储器并且可以容易地进行测试的装置。 在半导体存储器中，从存储器输出表示完成读/写准备的信号，使得用户在检测到该信号的输出之后，执行读/写数据。 为了便于诸如用于冗余位（校验位）的存储器单元测试，编码电路测试和解码电路测试的测试，本发明提供了可以彼此独立地进行布置的测试。

    Semiconductor memory for serial data access
    3.
    发明授权
    Semiconductor memory for serial data access 失效
    用于串行数据访问的半导体存储器

    公开(公告)号：US4701884A

    公开(公告)日：1987-10-20

    申请号：US896257

    申请日：1986-08-14

    申请人： Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara ,  Kiyoo Itoh ,  Hideo Nakamura ,  Osamu Minato

    发明人： Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara ,  Kiyoo Itoh ,  Hideo Nakamura ,  Osamu Minato

    IPC分类号： G11C11/56 ,  H01L27/108 ,  G11C13/00

    CPC分类号： G11C11/565 ,  H01L27/10805

    摘要： A semiconductor memory device is proposed wherein at least an array comprising a plurality of memory cells each having at least one capacity, a select mechanism for specifying the position of each memory cell, data lines connected to said memory cells for transmitting the data and a data writing and a data reading mechanisms are provided. The feature of this device lies in that the voltage generator for serially generating three or more values of the voltage which are different from each other and the means for applying said voltage to said memory cells are provided on the same semiconductor board as the same said memory cells, and as the said reading mechanism the column register is provided which, as said reading mechanism, has the mechanism for deciding the data, transfer gate which is provided between said deciding means and said data line, and the bias charge transfer mechanism which is provided between said transfer gate and said deciding mechanism, and having at least two or more memory elements for temporarily storing said decided data.

    摘要翻译： 提出了一种半导体存储器件，其中至少包括多个具有至少一个容量的存储单元的阵列，用于指定每个存储单元的位置的选择机构，连接到所述存储器单元的用于发送数据的数据线和数据 提供写入和数据读取机制。 该装置的特征在于，用于串联产生彼此不同的三个或更多个电压值的电压发生器和用于将所述电压施加到所述存储单元的装置设置在与所述存储器相同的半导体板上 并且作为所述读取机构，列寄存器被提供，其作为所述读取机构具有用于确定数据的机制，所述决定装置和所述数据线之间提供的传送门和作为所述读取机构的偏置电荷传送机构 提供在所述传送门和所述判定机构之间，并且具有用于临时存储所述决定的数据的至少两个或更多个存储器元件。

    Semiconductor memory having charge transfer device voltage amplifier
    5.
    发明授权
    Semiconductor memory having charge transfer device voltage amplifier 失效
    具有电荷转移装置电压放大器的半导体存储器

    公开(公告)号：US4636985A

    公开(公告)日：1987-01-13

    申请号：US648361

    申请日：1984-09-07

    申请人： Masakazu Aoki ,  Yoshinobu Nakagome ,  Masahi Horiguchi ,  Toshifumi Ozaki ,  Katsuhiro Shimohigashi ,  Shinichi Ikenaga

    发明人： Masakazu Aoki ,  Yoshinobu Nakagome ,  Masahi Horiguchi ,  Toshifumi Ozaki ,  Katsuhiro Shimohigashi ,  Shinichi Ikenaga

    IPC分类号： G11C7/06 ,  G11C7/22 ,  H01L27/108 ,  G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/06 ,  H01L27/108

    摘要： In a semiconductor memory in which a large number of memory cells are arrayed in the shape of a matrix, arrangements are provided for a high-sensitivity read-out. In one embodiment, a writing circuit, a voltage amplifier and a sense amplifier are successively connected to a data line that connects input and output ends of the memory cells in an identical row, with the voltage amplifier being formed as a CTD voltage amplifier that is composed of two charge transfer gates and a driving gate located between them. In accordance with another embodiment, a charge supplying circuit and a charge transfer circuit can be coupled between the memory cells and the sense amplifier to allow information transfer without any substantial loss.

    摘要翻译： 在其中以矩阵形式排列大量存储单元的半导体存储器中，提供了用于高灵敏度读出的布置。 在一个实施例中，写入电路，电压放大器和读出放大器连续地连接到连接存储器单元的输入和输出端相同行的数据线，电压放大器形成为CTD电压放大器 由两个电荷转移门和位于它们之间的驱动门组成。 根据另一个实施例，电荷供应电路和电荷转移电路可以耦合在存储器单元和读出放大器之间以允许信息传输而没有任何实质的损失。

    Address multiplexed dynamic RAM having a test mode capability
    8.
    发明授权
    Address multiplexed dynamic RAM having a test mode capability 失效
    地址复用动态RAM具有测试模式能力

    公开(公告)号：US5331596A

    公开(公告)日：1994-07-19

    申请号：US887802

    申请日：1992-05-26

    申请人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

    发明人： Kazuyuki Miyazawa ,  Katsuhiro Shimohigashi ,  Jun Etoh ,  Katsutaka Kimura

    IPC分类号： G11C11/401 ,  G01R31/317 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C11/407

    CPC分类号： G11C29/46 ,  G01R31/31701

    摘要： An address multiplexed dynamic random access memory (RAM) which has both a normal operation mode and a test mode capability is provided. The test mode is initiated in response to particular signal level combinations of both the row address strobe (RAS) and column address strobe (CAS) signals and the write enable (WE) signal. Since the signal level combinations employed in connection with implementing the test mode are unused in the normal operating mode of the dynamic RAM, additional external terminals are unneeded. This dynamic RAM employs multiplexing circuitry on both the input side as well as on the output side of the dynamic RAM, which multiplexing circuitry is controlled during normal operation by select signals from a decoder and during the test mode by a test signal which allows accessing of data at all of the common complementary data lines by the testing circuitry so as to determine whether there is consistency or inconsistency of the data being read out for testing.

    摘要翻译： 提供具有正常操作模式和测试模式能力的地址多路复用动态随机存取存储器（RAM）。 响应于行地址选通（＆upbar＆R）和列地址选通（＆upbar＆C）信号和写使能（＆upbar＆W）信号的特定信号电平组合，启动测试模式。 由于在动态RAM的正常操作模式中不使用与实现测试模式相关的信号电平组合，因此不需要额外的外部终端。 该动态RAM在动态RAM的输入侧和输出侧都采用多路复用电路，该复用电路在正常操作期间通过来自解码器的选择信号以及在测试模式期间通过允许访问的测试信号 通过测试电路在所有公共补充数据线上的数据，以便确定正在读出的用于测试的数据是否一致或不一致。

    Semiconductor memory
    9.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5119332A

    公开(公告)日：1992-06-02

    申请号：US515345

    申请日：1990-04-30

    申请人： Katsuhiro Shimohigashi ,  Hiroo Masuda ,  Hiroshi Kawamoto

    发明人： Katsuhiro Shimohigashi ,  Hiroo Masuda ,  Hiroshi Kawamoto

    IPC分类号： G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  H01L23/522 ,  H01L27/108

    CPC分类号： H01L27/108 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  H01L23/522 ,  H01L27/10805 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed to a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

    摘要翻译： 单元存储单元型的动态RAM集成电路设置有多条数据线，读出放大器，以与数据线相交的方式设置的多条字线，以及设置在数据线上的存储单元 数据线与字线之间的交点。 RAM包括P型半导体衬底和形成在衬底中的N型阱区。 存储单元设置在阱内，并且连接到日期线的读出放大器被构造成形成在半导体衬底中的一对N沟道MOSFET和形成在阱区中的一对P沟道MOSFET 。