公开(公告)号：US5512515A

公开(公告)日：1996-04-30

申请号：US910876

申请日：1992-07-09

申请人： Hideki Takeuchi ,  Koichiro Kawamura

发明人： Hideki Takeuchi ,  Koichiro Kawamura

IPC分类号： C23C16/18 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44

CPC分类号： C23C16/18 ,  H01L21/28556 ,  H01L21/76838 ,  H01L23/53219 ,  H01L2924/0002

摘要： A process comprising the steps of introducing an organic aluminum compound,including at least one of trialkylaluminum and dialkylhydriroaluminum, a copper chelate compound and a silane compound having one to three silicon atoms in the form of a gas mixture into a reactor holding a substrate heated to 250.degree. to 400.degree. C., forming an aluminum alloy thin film containing 0 to 5% copper and 0.1 to 2% silicon on the aforementioned substrate, and heat-treating the substrate formed with the aluminum thin film in an inert gas or hydrogen atmosphere at 400.degree. to 450.degree. C. In application of the present invention to a wiring technique of the semiconductor integrated circuit, it is possible to form a metallic thin film capable of completely smoothing a contact hole having a high aspect ratio.

摘要翻译： 一种方法，包括以下步骤：将包含三烷基铝和二烷基氢三铝的至少一种的有机铝化合物，铜螯合化合物和具有一个至三个气体混合物形式的硅原子的硅烷化合物引入加热到 250℃〜400℃，在上述基板上形成含有0〜5％的铜和0.1〜2％的硅的铝合金薄膜，在惰性气体或氢气氛中对形成有铝薄膜的基板进行热处理 在本发明的半导体集成电路的布线技术中，可以形成能够使纵横比高的接触孔完全平滑化的金属薄膜。

公开(公告)号：US5366919A

公开(公告)日：1994-11-22

申请号：US135532

申请日：1993-10-13

申请人： Kimiaki Tanaka ,  Hideki Takeuchi

发明人： Kimiaki Tanaka ,  Hideki Takeuchi

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L28/84 ,  H01L27/10808 ,  Y10S438/903

摘要： A method of making a memory cell having a transistor and a capacitor of a semiconductor memory device comprises the steps of: forming on a substrate on a surface of which the transistor is formed, an interlayer insulating film having a contact hole reaching a selected portion of the transistors; introducing a selected metal into a surface of the selected portion of the transistor exposed to the contact hole and a surface of the interlayer insulating film at portions thereof where a lower electrode of the capacitor is to be formed; forming a first conductive film having a pattern of the lower electrode of the capacitor by depositing a selected conductive material on the portions where the selected metal has been introduced; forming a capacitor insulating film on the first conductive film; and forming a second conductive film which provides an upper electrode of the capacitor on the capacitor insulating film; wherein the selected conductive material and the selected metal have such a relationship with each other that, when the first conductive layer is formed by depositing the selected conductive material on the portions where the selected metal has been introduced, the selected metal acts as a catalyzer to cause the selected conductive material to develop whisker crystal growth, thereby forming fine projections on an upper surface of the first conductive film.

摘要翻译： 制造具有半导体存储器件的晶体管和电容器的存储单元的方法包括以下步骤：在形成晶体管的表面上的衬底上形成具有到达所选择的部分的接触孔的层间绝缘膜 晶体管; 将选定的金属引入到暴露于接触孔的晶体管的选定部分的表面和在其中要形成电容器的下电极的部分处的层间绝缘膜的表面; 通过在选择的金属被引入的部分上沉积选定的导电材料，形成具有电容器的下电极图案的第一导电膜; 在所述第一导电膜上形成电容器绝缘膜; 以及形成在所述电容器绝缘膜上提供所述电容器的上电极的第二导电膜; 其中所选择的导电材料和所选择的金属彼此具有这样的关系：当通过在选择的金属被引入的部分上沉积所选择的导电材料形成第一导电层时，所选择的金属充当催化剂 导致所选择的导电材料产生晶须晶体生长，从而在第一导电膜的上表面上形成微小的突起。

公开(公告)号：US08399418B2

公开(公告)日：2013-03-19

申请号：US12810476

申请日：2008-12-24

申请人： Hideki Takeuchi ,  Eiji Tsuru

发明人： Hideki Takeuchi ,  Eiji Tsuru

IPC分类号： C07H17/02 ,  A61K31/7056 ,  A61P3/10

CPC分类号： C07H17/02

摘要： The present invention provides a novel form of 3-(3-{4-[3-(β-D-glucopyranosyloxy)-5-isopropyl-1H-pyrazol-4-ylmethyl]-3-methylphenoxy}propylamino)-2,2-dimethylpropionamide with improved storage stability. Since bis[3-(3-{4-[3-(β-D-glucopyranosyloxy)-5-isopropyl-1H-pyrazol-4-ylmethyl]-3-methylphenoxy}propylamino)-2,2-dimethylpropionamide]monosebacate has extremely excellent storage stability, it is useful as a drug substance. Furthermore, it shows an extremely good crystalline property and can be purified by a convenient method, and therefore is suitable for the industrial preparation.

摘要翻译： 本发明提供3-（3- {4- [3-（＆bgr。-D-吡喃葡萄糖氧基）-5-异丙基-1H-吡唑-4-基甲基] -3-甲基苯氧基}丙基氨基） 具有改进的储存稳定性的2-二甲基丙酰胺。 由于双[3-（3- {4- [3-（＆bgr-D-吡喃葡萄糖氧基）-5-异丙基-1H-吡唑-4-基甲基] -3-甲基苯氧基}丙基氨基）-2,2-二甲基丙酰胺] 具有非常优异的储存稳定性，作为药物有用。 此外，其显示出非常好的结晶性，并且可以通过方便的方法进行纯化，因此适用于工业制备。

公开(公告)号：US20100279962A1

公开(公告)日：2010-11-04

申请号：US12810476

申请日：2008-12-24

申请人： Hideki Takeuchi ,  Eiji Tsuru

发明人： Hideki Takeuchi ,  Eiji Tsuru

IPC分类号： A61K31/7056 ,  C07H17/02 ,  A61P3/10

CPC分类号： C07H17/02

摘要： The present invention provides a novel form of 3-(3-{4-[3-(β-D-glucopyranosyloxy)-5-isopropyl-1H-pyrazol-4-ylmethyl]-3-methylphenoxy}propylamino)-2,2-dimethylpropionamide with improved storage stability. Since bis[3-(3-{4-[3-(β-D-glucopyranosyloxy)-5-isopropyl-1H-pyrazol-4-ylmethyl]-3-methylphenoxy}propylamino)-2,2-dimethylpropionamide] monosebacate has extremely excellent storage stability, it is useful as a drug substance. Furthermore, it shows an extremely good crystalline property and can be purified by a convenient method, and therefore is suitable for the industrial preparation.

摘要翻译： 本发明提供3-（3- {4- [3-（＆bgr。-D-吡喃葡萄糖氧基）-5-异丙基-1H-吡唑-4-基甲基] -3-甲基苯氧基}丙基氨基） 具有改善的储存稳定性的2-二甲基丙酰胺。 由于双[3-（3- {4- [3-（＆bgr-D-吡喃葡萄糖氧基）-5-异丙基-1H-吡唑-4-基甲基] -3-甲基苯氧基}丙基氨基）-2,2-二甲基丙酰胺] 具有非常优异的储存稳定性，作为药物有用。 此外，其显示出非常好的结晶性，并且可以通过方便的方法进行纯化，因此适用于工业制备。

公开(公告)号：US07322936B2

公开(公告)日：2008-01-29

申请号：US10869127

申请日：2004-06-16

申请人： Hideki Takeuchi

发明人： Hideki Takeuchi

IPC分类号： A61B8/00

CPC分类号： G01S15/8925 ,  A61B8/483 ,  G01S7/52046 ,  G01S7/52079 ,  G01S15/8927 ,  G10K11/346 ,  Y10S128/916

摘要： In an ultrasound diagnosis apparatus, a plurality of sub arrays are defined on a 2D array transducer. The sub array shape pattern of each sub array is adaptively changed in accordance with the beam scanning direction. Each sub array is composed of a plurality of groups, each of which is composed of a plurality of transducer elements. With the change of sub array shape pattern in accordance with a beam scanning direction, the group shape pattern of each group also changes. The sub array shape changes for each sub array, and a variable region is determined by the largest outer edge of the shape changed. The variable regions partially overlap with each other among a plurality of sub arrays. On a 2D array transducer, a plurality of sub arrays are always closely coupled with each other even when each sub array shape is changed.

摘要翻译： 在超声波诊断装置中，在2D阵列换能器上定义多个子阵列。 每个子阵列的子阵列形状图案根据光束扫描方向自适应地改变。 每个子阵列由多个组组成，每组由多个换能器元件组成。 随着根据光束扫描方向的子阵列形状图案的改变，每组的组形状图案也改变。 每个子阵列的子阵列形状发生变化，可变区由形状变化的最大外边缘确定。 可变区域在多个子阵列中彼此部分重叠。 在2D阵列换能器上，即使当每个子阵列形状改变时，多个子阵列总是彼此紧密耦合。

公开(公告)号：US07064691B2

公开(公告)日：2006-06-20

申请号：US10213065

申请日：2002-08-07

申请人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

发明人： Hideki Takeuchi ,  Masami Murakata ,  Masaaki Yamada ,  Reiko Nojima ,  Takashi Ishioka ,  Mutsunori Igarashi

IPC分类号： H03M7/20 ,  H04B1/38 ,  H04L5/16 ,  H04H7/00

CPC分类号： H03K19/00361 ,  H03K17/162

摘要： A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.

摘要翻译： 噪声抑制电路包括内部电路，旁路电容器，第一和第二晶体管。 内部电路具有高低电平端子，低电平端子连接到低电平电源线。 内部电路提供使能和反相使能信号。 第一晶体管具有第一控制电极，一个主电极连接到高电平端子。 第一控制电极被提供有反相使能信号。 旁路电容器连接在第一晶体管的另一个主电极和低电平电源线之间。 第二晶体管连接在第一晶体管的另一个主电极和高电平电源线之间。 第二晶体管具有提供有使能信号的第二控制电极。 内部电路激活时，第二个晶体管不导通。

公开(公告)号：US20050270817A1

公开(公告)日：2005-12-08

申请号：US11075669

申请日：2005-03-10

申请人： Hideki Takeuchi ,  Takuya Fujimoto

发明人： Hideki Takeuchi ,  Takuya Fujimoto

IPC分类号： G11C8/00 ,  G11C16/10 ,  G11C29/00

CPC分类号： G11C16/10 ,  G11C29/789

摘要： A semiconductor memory device comprising: a first memory cell array including a plurality of memory cells, a first switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the first memory cell array, a latch circuit for latching the data transferred from the first switch circuit, a first write selector circuit for transferring the data transferred from the latch circuit, a first bit line connected to at least one of the plurality of memory cells and receiving the data transferred from the first write selector circuit, a second memory cell array including a plurality of memory cells that are different from the plurality of memory cells arranged in the first memory cell array, a second switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the second memory cell array, a second write selector circuit connected to the second switch circuit and transferring the data transferred from the second switch circuit, and a second bit line connected to at least one of the plurality of memory cells arranged in the second memory cell array.

摘要翻译： 一种半导体存储器件，包括：第一存储单元阵列，包括多个存储单元;第一开关电路，用于将被编程的数据传送到布置在第一存储单元阵列中的多个存储单元中的至少一个;锁存电路， 锁存从第一开关电路传送的数据，用于传送从锁存电路传送的数据的第一写选择器电路，连接到多个存储单元中的至少一个的第一位线，并接收从第一写选择器传送的数据 电路，包括与布置在第一存储单元阵列中的多个存储单元不同的多个存储单元的第二存储单元阵列;第二开关电路，用于将要编程的数据传送到多个存储单元中的至少一个存储单元 布置在第二存储单元阵列中的第二写选择器电路，连接到第二开关电路并传送数据转换 与第二开关电路错误，以及连接到布置在第二存储单元阵列中的多个存储单元中的至少一个的第二位线。

公开(公告)号：US20050237842A1

公开(公告)日：2005-10-27

申请号：US11110715

申请日：2005-04-21

申请人： Hideki Takeuchi ,  Takuya Fujimoto ,  Yoshiharu Hirata

发明人： Hideki Takeuchi ,  Takuya Fujimoto ,  Yoshiharu Hirata

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C7/18 ,  G11C16/04 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C29/80 ,  G11C7/18 ,  G11C16/0433 ,  G11C29/789

摘要： A semiconductor integrated circuit device comprises a semiconductor memory circuit including a memory cell array in which normal cells are integrated and a fuse circuit in which fuse cells that store operation information of the semiconductor memory circuit are integrated. The fuse cell is of a 2-transistor type memory cell which comprises a cell transistor having a charge storage layer and a selection transistor which selects the cell transistor.

摘要翻译： 一种半导体集成电路器件包括半导体存储器电路，其包括其中集成有正常单元的存储单元阵列和其中存储存储半导体存储器电路的操作信息的熔丝单元的熔丝电路。 熔丝单元是具有电荷存储层的单元晶体管和选择单元晶体管的选择晶体管的2晶体管型存储单元。

公开(公告)号：US06838333B2

公开(公告)日：2005-01-04

申请号：US10114989

申请日：2002-04-04

申请人： Hideki Takeuchi ,  Hirohiko Izumi

发明人： Hideki Takeuchi ,  Hirohiko Izumi

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/76895

摘要： A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

公开(公告)号：US06576860B2

公开(公告)日：2003-06-10

申请号：US10160243

申请日：2002-06-04

申请人： Chishio Koshimizu ,  Jun Ooyabu ,  Hideki Takeuchi ,  Akira Koshiishi

发明人： Chishio Koshimizu ,  Jun Ooyabu ,  Hideki Takeuchi ,  Akira Koshiishi

IPC分类号： B23K1000

CPC分类号： H01J37/32082 ,  H01J37/32165

摘要： A plasma processing method comprises the steps of supplying a low-frequency bias to a first electrode carrying a substrate, and supplying a high-frequency power to a second electrode facing the first electrode, wherein the low-frequency bias is supplied to the first electrode in advance of starting plasma by the energy of the high-frequency power, with an electric power sufficient to form an ion-sheath on the surface of the substrate.