公开(公告)号：US20090289368A1

公开(公告)日：2009-11-26

申请号：US12534478

申请日：2009-08-03

申请人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76847 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner at least partially within a metal interconnect. In one embodiment, a “U-shaped” EM preventing liner is provided that abuts a diffusion barrier that separates conductive material from the dielectric material. In another embodiment, a space is located between the “U-shaped” EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier.

摘要翻译： 提供了具有改进的电迁移（EM）可靠性的互连结构。 本发明的互连结构避免了通过将至少部分地在金属互连内部结合EM防止衬垫而由EM故障引起的电路死路。 在一个实施例中，提供了一种“U形”防EM衬垫，其与导电材料与电介质材料分离的扩散阻挡层相邻。 在另一个实施例中，空间位于“U形”EM防护衬垫和扩散阻挡层之间。 在另一个实施例中，提供了一个与扩散阻挡件相邻的水平EM衬垫。 在又一个实施例中，在水平EM衬垫和扩散阻挡层之间存在一个空间。

公开(公告)号：US07563704B2

公开(公告)日：2009-07-21

申请号：US11162666

申请日：2005-09-19

申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Lawrence A. Clevenger ,  Yun-Yu Wang ,  Daewon Yang

发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Lawrence A. Clevenger ,  Yun-Yu Wang ,  Daewon Yang

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76832 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.

摘要翻译： 提供了互连结构及其制造方法。 互连结构包括具有图案化开口的电介质层，设置在图案化开口中的金属特征以及覆盖金属特征的电介质盖。 电介质盖具有内部拉伸应力，该应力有助于避免在远离金属线的方向上发生电迁移，特别是当金属线具有拉伸应力时。

公开(公告)号：US20080203570A1

公开(公告)日：2008-08-28

申请号：US11679483

申请日：2007-02-27

申请人： Daniel C. Edelstein ,  Takeshi Nogami ,  Ping-Chuan Wang ,  Yun-Yu Wang ,  Chih-Chao Yang

发明人： Daniel C. Edelstein ,  Takeshi Nogami ,  Ping-Chuan Wang ,  Yun-Yu Wang ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76814 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures including a refractory metal collar at a copper wire and dielectric layer liner-less interface, and a related method, are disclosed. In one embodiment, a structure includes a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric layer; and a refractory metal collar extending from a side of the via and partially along the liner-less interface. Refractory metal collar prevents electromigration induced slit voiding by improving the interface around the via, and prevents void nucleation from occurring near the via. Also, the refractory metal collar provides electrical redundancy in the presence of voids around the via and dielectric layer liner-less interface.

摘要翻译： 公开了包括铜线处的难熔金属环和介电层无衬里界面的结构以及相关方法。 在一个实施例中，一种结构包括具有与其上方的介电层无衬层界面的铜线; 从铜线向上延伸穿过介电层的通孔; 以及从所述通孔的一侧延伸并部分地沿着所述无衬里界面延伸的耐火金属套环。 耐火金属轴环通过改善通孔周围的界面防止电迁移引起的狭缝空隙，并防止在通孔附近发生空隙成核。 此外，难熔金属套环在通孔和介电层无衬里界面周围存在空隙的情况下提供电冗余。

公开(公告)号：US07101784B2

公开(公告)日：2006-09-05

申请号：US11125549

申请日：2005-05-10

申请人： Lawrence A. Clevenger ,  Stephen E. Greco ,  Keith T. Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong H. Wong

发明人： Lawrence A. Clevenger ,  Stephen E. Greco ,  Keith T. Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong H. Wong

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

摘要翻译： 本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔 衬垫。 衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。 在等离子体处理期间，等离子体通过衬垫而不影响衬垫。 在等离子体处理之后，可以沉积另外的衬里材料。 此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。 该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。 绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。

公开(公告)号：US20050112864A1

公开(公告)日：2005-05-26

申请号：US10707122

申请日：2003-11-21

申请人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Erdem Kaltalioglu ,  Kaushik Kumar ,  Douglas La Tulipe, Jr. ,  Jochen Schacht ,  Andrew Simon ,  Terry Spooner ,  Yun-Yu Wang ,  Clement Wann ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Erdem Kaltalioglu ,  Kaushik Kumar ,  Douglas La Tulipe, Jr. ,  Jochen Schacht ,  Andrew Simon ,  Terry Spooner ,  Yun-Yu Wang ,  Clement Wann ,  Chih-Chao Yang

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

摘要翻译： 在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及 沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

公开(公告)号：US08294485B2

公开(公告)日：2012-10-23

申请号：US12699211

申请日：2010-02-03

申请人： Xu Ouyang ,  Yun-Yu Wang ,  Yunsheng Song

发明人： Xu Ouyang ,  Yun-Yu Wang ,  Yunsheng Song

IPC分类号： G01R31/02 ,  G01R31/08

CPC分类号： H01L27/1104 ,  G11C11/41 ,  G11C29/50 ,  G11C2029/5006 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method of detecting low-probability defects in large transistor arrays (such as large arrays of SRAM cells), where the defects manifest themselves as asymmetrical leakage in a transistor (such as a pulldown nFET in an SRAM cell). These defects are detected by creating one or more test arrays, identical in all regards to the large transistor arrays up until the contact and metallization layers. Leakage is measured by applying an appropriate off-state voltage (e.g., 0V) by a common connection to all of the gates of the transistors in the test array, then measuring the aggregate drain/source leakage current, both forward and reverse (e.g., first grounded source and positively biased drain, then grounded drain and positively biased source) comparing the difference between the two leakage current measurements.

摘要翻译： 检测大晶体管阵列（例如大量SRAM单元阵列）中的低概率缺陷的方法，其中缺陷在晶体管（例如，SRAM单元中的下拉nFET）中表现为非对称泄漏。 通过创建一个或多个测试阵列来检测这些缺陷，所有这些测试阵列在大量晶体管阵列上相同，直到接触和金属化层。 通过与测试阵列中的晶体管的所有栅极的公共连接施加适当的截止状态电压（例如，0V）来测量泄漏，然后测量正向和反向的汇总漏极/漏极电流（例如， 第一接地源和正偏置漏极，然后接地漏极和正偏置源）比较两个漏电流测量值之间的差异。

公开(公告)号：US20120184075A1

公开(公告)日：2012-07-19

申请号：US13009020

申请日：2011-01-19

申请人： Anthony G. Domenicucci ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel C. Ontalus ,  Yun-Yu Wang

发明人： Anthony G. Domenicucci ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel C. Ontalus ,  Yun-Yu Wang

IPC分类号： H01L21/336 ,  H01L21/84

CPC分类号： H01L29/7847 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.

摘要翻译： 形成半导体器件的方法包括将非晶化物质注入晶体半导体衬底中，所述衬底具有在其上形成的晶体管栅极结构。 碳被植入到基底的非晶化区域中，其特定的植入条件被定制，使得碳类的峰值浓度与堆垛层错的结束一致，其中在重结晶退火期间产生堆垛层错。 植入的碳引脚部分位错，以防止位错从堆垛层错的末端脱离，并移动到晶体管栅极结构正下方的衬底区域。 这消除了导致设备泄漏失败的缺陷。

公开(公告)号：US20100025819A1

公开(公告)日：2010-02-04

申请号：US12185375

申请日：2008-08-04

申请人： Anthony G. Domenicucci ,  Terence L. Kane ,  Michael Tenney ,  Yun-Yu Wang

发明人： Anthony G. Domenicucci ,  Terence L. Kane ,  Michael Tenney ,  Yun-Yu Wang

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L23/5228 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of metal than the first metal semiconductor alloy. Due to the stoichiometric differences between the first and second metal semiconductor alloys, the link portion has a higher resistance after programming than prior to programming. The shift in electrical resistance well controlled, which is advantageously employed to as a programmable precision resistor.

摘要翻译： 第一电极和第二电极之间的连接部分包括半导体连接部分和包括第一金属半导体合金的金属半导体合金连接部分。 电脉冲将整个连接部分转换成具有比第一金属半导体合金低的金属浓度的第二金属半导体合金。 由于第一和第二金属半导体合金之间的化学计量差异，链接部分在编程之后具有比编程之前更高的电阻。 良好控制的电阻的偏移，其有利地用作可编程精密电阻器。

公开(公告)号：US20090181532A1

公开(公告)日：2009-07-16

申请号：US11971996

申请日：2008-01-10

申请人： David P. Colon ,  Bradley P. Jones ,  Ramona Kei ,  Raymond G. Knauss ,  Richard P. Volant ,  Yun-Yu Wang

发明人： David P. Colon ,  Bradley P. Jones ,  Ramona Kei ,  Raymond G. Knauss ,  Richard P. Volant ,  Yun-Yu Wang

IPC分类号： H01L21/44

CPC分类号： H01L24/03 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014

摘要： An interconnect structure having an incomplete via opening is processed to deepen a via opening and to expose a metal line. In case the interconnect structure comprises a metal pad or a blanket metal layer, the metal pad or the metal layer is removed selective to an underlying dielectric layer to expose the incomplete via opening. Another dielectric layer is formed within the incomplete via opening to compensated for differences in the total dielectric thickness above the metal line relative to an optimal dielectric stack. A photoresist is applied thereupon and patterned. An anisotropic etch process for formation of a normal via opening may be employed with no or minimal modification to form a proper via opening and to expose the metal line. A metal pad is formed upon the metal line so that electrical contact is provided between the metal pad and the metal line.

摘要翻译： 处理具有不完全通孔的互连结构以加深通孔开口并露出金属线。 在互连结构包括金属焊盘或覆盖金属层的情况下，金属焊盘或金属层被选择性地移除到下面的电介质层以暴露不完全通孔。 在不完全通孔内部形成另一个介电层，以补偿相对于最佳电介质叠层的金属线上方的总电介质厚度的差异。 在其上施加光致抗蚀剂并图案化。 可以采用用于形成正常通孔的各向异性蚀刻工艺，没有或最小的修改以形成适当的通孔开口并露出金属线。 在金属线上形成金属焊盘，使得金属焊盘和金属线之间提供电接触。

公开(公告)号：US07504336B2

公开(公告)日：2009-03-17

申请号：US11419300

申请日：2006-05-19

申请人： Robert J. Purtell ,  Henry K. Utomo ,  Yun-Yu Wang ,  Haining S. Yang

发明人： Robert J. Purtell ,  Henry K. Utomo ,  Yun-Yu Wang ,  Haining S. Yang

IPC分类号： H01L21/44

CPC分类号： H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7845

摘要： The present invention provides a method of fabricating semiconductor device comprising at least one field effect transistor (FET) having source and drain (S/D) metal silicide layers with intrinsic tensile or compressive stress. First, a metal layer containing a silicide metal M is formed over S/D regions of a FET, followed by a first annealing step to form S/D metal silicide layers that comprise a metal silicide of a first phase (MSix). A silicon nitride layer is then formed over the FET, followed by a second annealing step. During the second annealing step, the metal silicide is converted from the first phase (MSix) into a second phase (MSiy) with x

摘要翻译： 本发明提供一种制造半导体器件的方法，该方法包括至少一个场效应晶体管（FET），其具有具有固有拉伸或压缩应力的源和漏（S / D）金属硅化物层。 首先，在FET的S / D区域上形成含有硅化物金属M的金属层，接着进行第一退火工序，形成包含第一相金属硅化物（MSix）的S / D金属硅化物层。 然后在FET上形成氮化硅层，接着进行第二退火步骤。 在第二退火步骤期间，金属硅化物从第一相（MSix）转换成具有x