公开(公告)号：US20140281175A1

公开(公告)日：2014-09-18

申请号：US14265400

申请日：2014-04-30

Applicant: Macronix International Co., Ltd.

Inventor： Lung-Yi Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Shuo-Nan Hung ,  Han-Sung Chen

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F11/00 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C16/10 ,  G11C16/105 ,  G11C2211/5648

Abstract: A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.

Abstract translation: 提供了一种用于多级单元（MLC）闪速存储器的程序方法。 存储器阵列包括对应于各个页面的多个页面和多个配对页面。 程序方法包括以下步骤。 首先，获得程序地址命令。 接下来，确定与配对页中的任何一个对应的程序地址命令。 当程序地址命令对应于对应于页面中的第一页的第一配对页面时，在配对页面中，复制存储在第一页面中的非易失性存储器的数据。 之后，第一个配对的页面被编程。

公开(公告)号：US20140269074A1

公开(公告)日：2014-09-18

申请号：US13950942

申请日：2013-07-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Lung Yi KUO ,  Hsin Yi Ho ,  Chun Hsiung Hung ,  Shuo-Nan Hung ,  Han-Sung Chen ,  Shih-Chou Juan

IPC: G11C16/10 ,  G11C29/04

CPC classification number: G11C16/10 ,  G11C29/808 ,  G11C29/82 ,  G11C2029/4402

Abstract: A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged.

Abstract translation: 一种用于编程包括多个块的非易失性存储器的方法，每个块包括多个部分，每个部分包括至少一个页面，并且每个页面包括多个存储器单元。 该方法包括根据损坏部分表检查多个部分的当前部分，以确定当前部分是否损坏。 损坏的部分表记录有关内存中的部分是好还是损坏的信息。 该方法还包括如果当前部分没有损坏，则使用当前部分进行编程。

公开(公告)号：US20140258811A1

公开(公告)日：2014-09-11

申请号：US13951130

申请日：2013-07-25

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Ching Liu ,  Chi Lo ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G06F11/10 ,  G06F12/00

CPC classification number: G06F11/1044 ,  G06F11/1008 ,  G06F11/1068 ,  G11B20/1833 ,  G11C7/1006

Abstract: A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.

Abstract translation: 一种设备包括存储与数据相对应的数据和纠错码ECC的存储器阵列，以及存储器阵列和输入/输出数据路径之间的多级缓冲器结构。 存储器阵列包括用于页模式操作的多条数据线。 缓冲器结构包括：第一缓冲器，其具有连接到用于数据页的多条数据线中的相应数据线的存储单元;耦合到第一缓冲器中用于存储至少一页数据的存储单元的第二缓冲器;以及 耦合到第二缓冲器和输入/输出数据路径的第三缓冲器。 该设备包括耦合到多级缓冲器的逻辑，用于在存储器阵列和通过多级缓冲器的输入/输出路径之间的移动期间在页面读取和页面写入操作中的至少一个上执行数据页面上的逻辑处理。

公开(公告)号：US08787078B2

公开(公告)日：2014-07-22

申请号：US14105920

申请日：2013-12-13

Applicant: Macronix International Co., Ltd.

Inventor： Chun Hsiung Hung ,  Shuo-Nan Hung ,  Tseng-Yi Liu

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418

Abstract: Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution.

Abstract translation: NAND存储器的各个方面包括控制电路，该控制电路通过测量在串联的第一端和第二端之间流动的电流来将读偏置装置施加到多个字线以读取存储在多个存储单元上的选定数据值 的记忆细胞。 读取偏置布置被施加到多个字线的字线仅施加小于第二阈值电压分布的第二最大值的字线电压。

公开(公告)号：US20130314997A1

公开(公告)日：2013-11-28

申请号：US13959780

申请日：2013-08-06

Applicant: Macronix International Co., Ltd.

Inventor： Chung-Kuang Chen ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G11C16/04

CPC classification number: G11C16/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/32

Abstract: A memory access method is applied in a memory controller for accessing a memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes: enabling the string select signal and disabling the string select signal before a read phase.

Abstract translation: 存储器访问方法应用于存储器控制器中，用于访问存储器阵列，包括由字符串选择信号全局控制的多个相应的选择开关。 存储器访问方法包括：在读取阶段之前启用字符串选择信号并禁用字符串选择信号。