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    Memory cell imprint avoidance
    51.
    发明授权
    Memory cell imprint avoidance 有权

    公开(公告)号：US10978128B2

    公开(公告)日：2021-04-13

    申请号：US16586334

    申请日：2019-09-27

    Applicant: Micron Technology, Inc.

    Inventor： Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy ,  Kirk Prall ,  Ferdinando Bedeschi

    IPC: G11C11/22 ,  G11C29/52 ,  G06F11/10

    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

    Cell performance recovery using cycling techniques
    53.
    发明授权
    Cell performance recovery using cycling techniques 有权

    公开(公告)号：US10706906B2

    公开(公告)日：2020-07-07

    申请号：US16044310

    申请日：2018-07-24

    Applicant: Micron Technology, Inc.

    Inventor： Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy

    IPC: G11C11/22

    Abstract: Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of memory cell. For example, a ferroelectric memory cell may enter a fatigue state after a number of access operations are performed at an access rate. After the number of access operations have been performed at the access rate, a fatigue state of the ferroelectric memory cell may be identified and the series of pulses may be applied to the ferroelectric capacitor at a different (e.g., higher) rate. For instance, a delay between pulses of the series of pulses may be shorter than the delay between access operations of the ferroelectric memory cell.

    Writing to cross-point non-volatile memory
    55.
    发明授权
    Writing to cross-point non-volatile memory 有权

    公开(公告)号：US10153026B2

    公开(公告)日：2018-12-11

    申请号：US15858831

    申请日：2017-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Bei Wang ,  Alessandro Calderoni ,  Wayne Kinney ,  Adam Johnson ,  Durai Vishak Nirmal Ramaswamy

    IPC: G11C11/22 ,  G11C11/56 ,  H01L27/11507 ,  G11C14/00 ,  H01L27/11502

    Abstract: Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.

    MEMORY CELL IMPRINT AVOIDANCE
    60.
    发明申请
    MEMORY CELL IMPRINT AVOIDANCE 审中-公开

    公开(公告)号：US20170365323A1

    公开(公告)日：2017-12-21

    申请号：US15645106

    申请日：2017-07-10

    Applicant: Micron Technology, Inc.

    Inventor： Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy ,  Kirk Prall ,  Ferdinando Bedeschi

    IPC: G11C11/22 ,  G06F11/10 ,  G11C29/52

    CPC classification number: G11C11/2275 ,  G06F11/1048 ,  G06F11/1068 ,  G11C11/221 ,  G11C11/2273 ,  G11C29/52

    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

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