公开(公告)号：US20210264972A1

公开(公告)日：2021-08-26

申请号：US16797432

申请日：2020-02-21

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Hari Giduturi ,  Fabio Pellizzer

IPC: G11C11/56 ,  G11C11/409 ,  G11C11/4074 ,  G11C29/50

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

公开(公告)号：US10396795B1

公开(公告)日：2019-08-27

申请号：US15926548

申请日：2018-03-20

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hari Giduturi

IPC: H03K19/0185 ,  H03K17/10 ,  H03K5/003 ,  H03K5/00

Abstract: Methods, systems, and devices for shifting voltage levels of electrical signals and more specifically for boosted high-speed level shifting are described. A boosted level shifter may include a driver circuit that generates a drive signal having a greater voltage swing than an input signal, and the drive signal may drive the gate of a pull-up transistor within the boosted level shifter. The lower bound of the drive signal may in some cases be a negative voltage. Driving the pull-up transistor with a drive signal having a greater voltage swing than the input signal may improve the operational speed and current-sourcing capability of the pull-up transistor, which may provide speed and efficiency benefits.

公开(公告)号：US20190080756A1

公开(公告)日：2019-03-14

申请号：US16190563

申请日：2018-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Hari Giduturi ,  Mingdong Cui

IPC: G11C13/00 ,  G11C29/50

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/50004 ,  G11C2013/009 ,  G11C2029/5004 ,  G11C2213/72 ,  G11C2213/76

Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. All example apparatus, may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.

公开(公告)号：US20180090204A1

公开(公告)日：2018-03-29

申请号：US15828402

申请日：2017-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Hari Giduturi ,  Mingdong Cui

IPC: G11C13/00 ,  G11C29/50

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/50004 ,  G11C2013/009 ,  G11C2029/5004 ,  G11C2213/72 ,  G11C2213/76

Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.

公开(公告)号：US09627052B1

公开(公告)日：2017-04-18

申请号：US14950413

申请日：2015-11-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Hari Giduturi ,  Mingdong Cui

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/50004 ,  G11C2013/009 ,  G11C2029/5004 ,  G11C2213/72 ,  G11C2213/76

Abstract: Apparatuses and methods are described herein for limiting current in threshold switching memories. In an example, an apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.

公开(公告)号：US12176031B2

公开(公告)日：2024-12-24

申请号：US17723673

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jason M. Brown

IPC: G11C11/16 ,  G11C13/00 ,  H01L25/065

Abstract: A memory device includes a substrate with two or more memory die stacked in a three-dimensional stacked (3DS) configuration. The memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The two or more memory die each include its own plurality of memory cells. Furthermore, each of the two or more memory die include a local control circuitry configured to receive or transmit a divided clock that is based on the clock.

公开(公告)号：US20240331757A1

公开(公告)日：2024-10-03

申请号：US18740242

申请日：2024-06-11

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C11/4076 ,  G11C5/04 ,  G11C5/06 ,  H01L25/065

CPC classification number: G11C11/4076 ,  G11C5/06 ,  H01L25/0657 ,  G11C5/04 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: A packaged memory device can include a primary memory die coupled to a shared intra-package communication bus and coupled to an external host device using a host interface bus, and the host interface bus can include a host clock channel. The memory device can include multiple secondary dies coupled to the intra-package communication bus, and each of the secondary dies can be configured to receive the same messages from the primary memory die using the intra-package communication bus. The primary memory die can send a first message to, or receive a first message from, a particular one of the secondary dies using the intra-package communication bus, and the first message can include a first chip identification field that exclusively indicates the particular one of the secondary dies.

公开(公告)号：US20240265965A1

公开(公告)日：2024-08-08

申请号：US18639690

申请日：2024-04-18

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jeffrey E. Koelling ,  Mingdong Cui ,  Ramachandra Rao Jogu

IPC: G11C13/00 ,  H03K19/20

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  G11C2213/15 ,  H03K19/20

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

公开(公告)号：US12051463B2

公开(公告)日：2024-07-30

申请号：US17864004

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Jeffrey E. Koelling ,  Hari Giduturi ,  Riccardo Muzzetto ,  Corrado Villa

IPC: G11C13/00

CPC classification number: G11C13/0026 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033

Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

公开(公告)号：US11972147B2

公开(公告)日：2024-04-30

申请号：US17723773

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory system can include a stack of memory dies such as including a primary die and two or more secondary dies. The primary die can communicate with an external host device and with the secondary dies. In an example, the primary die can issue a command to the secondary dies using a first command message that includes an opcode field specifying a memory operation, a first chip identification field specifying a selected first die of the secondary dies, and one or more operands. In an example, each of the secondary dies receives the same first command message.