中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

73 records (took 0.026 seconds)

    APPARATUSES AND METHODS FOR ADAPTIVE CONTROL OF MEMORY
    51.
    发明申请
    APPARATUSES AND METHODS FOR ADAPTIVE CONTROL OF MEMORY 审中-公开

    公开(公告)号：US20180322039A1

    公开(公告)日：2018-11-08

    申请号：US16030600

    申请日：2018-07-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： David A. Roberts ,  J. Thomas Pawlowski ,  Robert Walker

    IPC: G06F12/02 ,  G06F13/16

    Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data.

    Apparatuses and methods for pre-fetching and write-back for a segmented cache memory
    52.
    发明授权
    Apparatuses and methods for pre-fetching and write-back for a segmented cache memory 有权

    公开(公告)号：US10019369B2

    公开(公告)日：2018-07-10

    申请号：US15436570

    申请日：2017-02-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： David Roberts ,  J. Thomas Pawlowski

    IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/0811

    CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F12/0895 ,  G06F2212/283 ,  G06F2212/602 ,  Y02D10/13

    Abstract: Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested information is read from memory. Additional information is read from memory based on the transaction history, wherein the requested information and the additional information are read together from memory. The requested information is cached in a segment of a cache line of the cache block and the additional information in cached another segment of the cache line. In another example, the transaction history is also updated to reflect the caching of the requested information and the additional information. In another example, read masks associated with the cache tag are referenced for the transaction history, the read masks identifying segments of a cache line previously accessed.

    Apparatuses and methods for pre-fetching and write-back for a segmented cache memory
    55.
    发明授权
    Apparatuses and methods for pre-fetching and write-back for a segmented cache memory 有权

    公开(公告)号：US09612972B2

    公开(公告)日：2017-04-04

    申请号：US13692907

    申请日：2012-12-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： David Roberts ,  J. Thomas Pawlowski

    IPC: G06F12/00 ,  G06F12/0895

    CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F12/0895 ,  G06F2212/283 ,  G06F2212/602 ,  Y02D10/13

    Abstract: Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested information is read from memory. Additional information is read from memory based on the transaction history, wherein the requested information and the additional information are read together from memory. The requested information is cached in a segment of a cache line of the cache block and the additional information in cached another segment of the cache line. In another example, the transaction history is also updated to reflect the caching of the requested information and the additional information. In another example, read masks associated with the cache tag are referenced for the transaction history, the read masks identifying segments of a cache line previously accessed.

    Pattern-recognition processor with matching-data reporting module
    58.
    发明授权
    Pattern-recognition processor with matching-data reporting module 有权
    具有匹配数据报告模块的模式识别处理器

    公开(公告)号：US09026485B2

    公开(公告)日：2015-05-05

    申请号：US14269853

    申请日：2014-05-05

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski

    IPC: G06F17/00 ,  G06N5/02 ,  G06F7/02 ,  G06K9/62

    CPC classification number: G06N5/025 ,  G06F7/02 ,  G06F2207/025 ,  G06K9/62

    Abstract: Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include a matching-data reporting module, which may have a buffer and a match event table. The buffer may be coupled to a data stream and configured to store at least part of the data stream, and the match event table may be configured to store data indicative of a buffer location corresponding with a start of a search criterion being satisfied.

    Abstract translation: 公开了方法和装置，其中包括模式识别处理器的装置。 模式识别处理器可以包括匹配数据报告模块，其可以具有缓冲器和匹配事件表。 缓冲器可以耦合到数据流并且被配置为存储数据流的至少一部分，并且匹配事件表可以被配置为存储指示与满足搜索条件的开始相对应的缓冲器位置的数据。

    Multi-port memory and operation
    59.
    发明授权
    Multi-port memory and operation 有权
    多端口内存和操作

    公开(公告)号：US08930643B2

    公开(公告)日：2015-01-06

    申请号：US14299237

    申请日：2014-06-09

    Applicant: Micron Technology, Inc.

    Inventor： Dan Skinner ,  J. Thomas Pawlowski

    IPC: G06F13/00 ,  G06F13/28 ,  G11C7/10

    CPC classification number: G06F13/1631 ,  G06F13/16 ,  G06F13/1636 ,  G11C7/1075 ,  G11C8/16 ,  Y02D10/14

    Abstract: Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.

    Abstract translation: 具有用于在端口之间传递命令的附加控制总线的多端口存储器具有可被配置为响应从外部控制总线接收的命令或从附加控制总线接收的命令的各个端口。 这有助于端口的各种组合来改变存储器的带宽或延迟，以便于针对不同的应用定制性能特征。

    Memory system and method using partial ECC to achieve low power refresh and fast access to data
    60.
    发明授权
    Memory system and method using partial ECC to achieve low power refresh and fast access to data 有权
    使用部分ECC的内存系统和方法实现低功耗刷新和快速访问数据

    公开(公告)号：US08832522B2

    公开(公告)日：2014-09-09

    申请号：US13746504

    申请日：2013-01-22

    Applicant: Micron Technology, Inc.

    Inventor： J. Thomas Pawlowski

    IPC: G11C29/00 ,  H03M13/00 ,  G06F11/10 ,  G11C11/406 ,  G11C29/04

    CPC classification number: G06F11/1076 ,  G06F11/1008 ,  G06F11/1044 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062 ,  G11C2211/4067

    Abstract: A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

    Abstract translation: DRAM存储器件包括几组存储器单元，每个存储单元被分成第一组和第二组存储器单元。 可以以相对较慢的速率刷新第一组中的存储器单元以减少DRAM器件消耗的功率。 DRAM设备中的错误检查和校正电路校正由相对较慢的刷新率引起的第一组存储器单元中的任何数据保留错误。 第二组中的存储单元以正常速率刷新，速度足够快，不会发生数据保留错误。 可以对DRAM装置中的模式寄存器进行编程，以选择第二组存储器单元的大小。

Patent Agency Ranking