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公开(公告)号：US11775181B2
公开(公告)日：2023-10-03
申请号：US17708735
申请日：2022-03-30
Applicant: Micron Technology, Inc.
Inventor： Xiangang Luo , Harish Reddy Singidi , Ting Luo , Kishore Kumar Muchherla
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0679
Abstract: Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system, the error recovery data structure storing indications that specific CWs are correctable or not correctable by specific error handing (EH) steps of a set of multiple EH steps, and determine an order of EH steps for the storage system based on the error recovery data structure. Maintaining the error recovery data structure can include determining if each CW of the set of CWs is correctable by a specific EH step, storing indications of CWs determined correctable by the specific EH step in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.
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公开(公告)号：US20230205450A1
公开(公告)日：2023-06-29
申请号：US18111213
申请日：2023-02-17
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Guang Hu , Ting Luo , Tao Liu
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A method includes performing a first read operation involving a set of memory cells using a first voltage, determining a quantity of bits associated with the set of memory cells based on the first read operation, performing a second read operation involving the set of memory cells using a second voltage that is greater than the first voltage when the quantity of bits is above a threshold quantity of bits for the set of memory cells, and performing the second read operation involving the set of memory cells using a third voltage that is less than the first voltage when the quantity of bits is below the threshold quantity of bits for the set of memory cells.
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公开(公告)号：US20230185479A1
公开(公告)日：2023-06-15
申请号：US18105043
申请日：2023-02-02
Applicant: Micron Technology, Inc.
Inventor： Tao Liu , Ting Luo , Jianmin Huang
CPC classification number: G06F3/0655 , G06F3/0679 , G06F3/0604 , G11C16/349
Abstract: A method includes determining a first memory access count threshold for a first word line of a block of memory cells and determining a second memory access count threshold for a second word line of the block of memory cells. The second memory access count threshold can be greater than the first memory access count threshold. The method can further include incrementing a memory block access count corresponding to the block of memory cells that includes the first word line and the second word line in response to receiving a memory access command and refreshing the first word line when the memory block access count corresponding to the block of memory cells is equal to the first memory access count threshold.
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公开(公告)号：US11675411B2
公开(公告)日：2023-06-13
申请号：US17470506
申请日：2021-09-09
Applicant: Micron Technology, Inc.
Inventor： Giuseppe D'Eliseo , Xiangang Luo , Ting Luo , Jianmin Huang
IPC: G06F1/3206 , G06F12/06 , G06F12/02 , G06F1/3296
CPC classification number: G06F1/3206 , G06F1/3296 , G06F12/0246 , G06F12/06
Abstract: Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area and an address of the first P2L data structure can be stored in the second P2L data structure.
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公开(公告)号：US11670381B2
公开(公告)日：2023-06-06
申请号：US17313249
申请日：2021-05-06
Applicant: Micron Technology, Inc.
Inventor： Ashutosh Malshe , Kishore Kumar Muchherla , Harish Reddy Singidi , Peter Sean Feeley , Sampath Ratnam , Kulachet Tanpairoj , Ting Luo
CPC classification number: G11C16/26 , G11C16/04 , G11C16/0483 , G11C16/28 , G11C16/349 , G11C29/021 , G11C29/028 , G11C16/08 , G11C16/24 , G11C2207/2254
Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
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Patent Agency Ranking
公开(公告)号：US20220276928A1
公开(公告)日：2022-09-01
申请号：US17746754
申请日：2022-05-17
Applicant: Micron Technology, Inc.
Abstract: An apparatus includes a memory sub-system comprising a plurality of memory blocks and a memory block defect detection component. The memory block defect detection component is to set, for a memory block among the plurality of memory blocks, a first block defect detection rate and determine whether the first block defect detection rate is greater than a threshold block defect detection rate for the at least one memory block. In response to a determination that the first block defect detection rate is greater than the threshold block defect detection rate for the memory block, the memory block defect detection component is to assert a program command on the memory block determine whether a program operation associated with assertion of the program command on the at least one memory block is successful. In response to a determination the program operation is unsuccessful, the memory block defect detection component is to determine that a failure involving a plane associated with the memory block and another plane of the memory sub-system has occurred.
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公开(公告)号：US11340982B1
公开(公告)日：2022-05-24
申请号：US17087334
申请日：2020-11-02
Applicant: Micron Technology, Inc.
Abstract: An apparatus includes a memory sub-system comprising a plurality of memory blocks and a memory block defect detection component. The memory block defect detection component is to set, for a memory block among the plurality of memory blocks, a first block defect detection rate and determine whether the first block defect detection rate is greater than a threshold block defect detection rate for the at least one memory block. In response to a determination that the first block defect detection rate is greater than the threshold block defect detection rate for the memory block, the memory block defect detection component is to assert a program command on the memory block determine whether a program operation associated with assertion of the program command on the at least one memory block is successful. In response to a determination the program operation is unsuccessful, the memory block defect detection component is to determine that a failure involving a plane associated with the memory block and another plane of the memory sub-system has occurred.
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公开(公告)号：US20220138073A1
公开(公告)日：2022-05-05
申请号：US17085671
申请日：2020-10-30
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Tao Liu , Christopher J. Bueb , Eric Yuen , Cheng Cheng Ang
Abstract: A method includes monitoring a temperature of a memory component of a memory sub-system to determine that the temperature of the memory component corresponds to a first monitored temperature value; writing data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the first monitored temperature value; determining that the first monitored temperature value exceeds a threshold temperature range; monitoring the temperature of the memory component of the memory sub-system to determine that the temperature of the memory component corresponds to a second monitored temperature value that is within the threshold temperature range; and rewriting the data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the second monitored temperature value.
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公开(公告)号：US20220130457A1
公开(公告)日：2022-04-28
申请号：US17572209
申请日：2022-01-10
Applicant: Micron Technology, Inc.
Inventor： Sebastien Andre Jean , Ting Luo
Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.
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公开(公告)号：US20210191807A1
公开(公告)日：2021-06-24
申请号：US16723836
申请日：2019-12-20
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Falgun G. Trivedi , Harish Reddy Singidi , Xiangang Luo , Preston Allen Thomson , Ting Luo , Jianmin Huang
IPC: G06F11/10 , G06F11/07 , G06F12/02 , G06F12/0882
Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.
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