公开(公告)号：US12020747B2

公开(公告)日：2024-06-25

申请号：US17511802

申请日：2021-10-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Feng-Min Lee ,  Yung-Chun Li

IPC: G11C11/00 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/10

Abstract: A non-volatile memory and a programming method thereof are provided. The programming method of the non-volatile memory includes the following steps. A coarse programming procedure is performed for programing all of a plurality of memory cells at an erase state to 2{circumflex over ( )}N−1 or 2{circumflex over ( )}N program states. N is a positive integer. A fine programming procedure is performed for pushing all of memory cells into 2{circumflex over ( )}N−1 or 2{circumflex over ( )}N verify levels.

公开(公告)号：US11955202B2

公开(公告)日：2024-04-09

申请号：US18055855

申请日：2022-11-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ming-Hsiu Lee ,  Po-Hao Tseng

IPC: G11C15/00 ,  G11C7/10 ,  G11C15/04

CPC classification number: G11C7/1063 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/1096 ,  G11C15/04

Abstract: A multilevel content addressable memory, a multilevel coding method and a multilevel searching method are provided. The multilevel coding method includes the following steps. A highest decimal value of a multilevel-bit binary data is obtained. A length of a digital string data is set as being the highest decimal value of the multilevel-bit binary data. The multilevel-bit binary data is converted into the digital string data. If a content of the multilevel-bit binary data is an exact value, a number of an indicating bit in the digital string data is the exact value.

公开(公告)号：US11804269B2

公开(公告)日：2023-10-31

申请号：US18073366

申请日：2022-12-01

Applicant: MACRONIX International Co., Ltd.

Inventor： Feng-Min Lee ,  Po-Hao Tseng ,  Yu-Hsuan Lin ,  Ming-Hsiu Lee

IPC: G11C16/30 ,  H01L29/788 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  H01L29/792 ,  H01L29/423 ,  G11C11/56 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/30 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  H01L29/42392 ,  H01L29/7885 ,  H01L29/792 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.

公开(公告)号：US11756620B2

公开(公告)日：2023-09-12

申请号：US17463607

申请日：2021-09-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: G11C15/00 ,  G11C15/04

CPC classification number: G11C15/046

Abstract: A memory cell for an analog content-addressable memory is provided. The memory cell includes an N-type transistor, a P-type transistor, and a current control circuit. The gate of the N-type transistor is configured to receive a first input signal. The gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor. The current control circuit is configured to generate at least one passing current. When the input voltages of the first input signal and the second input signal are within a matching range, the N-type transistor and the P-type transistor are turned on, and the passing current is substantially a fixed current value. The matching range is related to the threshold voltages of the N-type transistor and the P-type transistor, and the fixed current value.

公开(公告)号：US11587617B2

公开(公告)日：2023-02-21

申请号：US17333046

申请日：2021-05-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Feng-Min Lee ,  Ming-Hsiu Lee ,  Liang-Yu Chen ,  Yun-Yuan Wang

IPC: G11C15/04 ,  G11C11/404 ,  G11C16/04 ,  G11C15/00

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.

公开(公告)号：US11586418B2

公开(公告)日：2023-02-21

申请号：US16807194

申请日：2020-03-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Ming-Hsiu Lee ,  Yu-Hsuan Lin

IPC: G06F7/58 ,  G06F9/30 ,  G06F1/14 ,  G06F1/10

Abstract: A random number generator, a random number generating circuit, and a random number generating method are provided. The random number generating circuit includes the random number generator and executes the random number generating method. The random number generator includes a shift register having N storage elements and a combinational logic circuit. The N storage elements receive a random seed in a static state and repetitively perform a bit shift operation in a plurality of clock cycles. The combinational logic circuit generates an output sequence based on the random seed and a random bitstream received from an external source.

公开(公告)号：US20220246218A1

公开(公告)日：2022-08-04

申请号：US17166484

申请日：2021-02-03

Applicant: MACRONIX International Co., Ltd.

Inventor： Feng-Min Lee ,  Po-Hao Tseng ,  Yu-Hsuan Lin ,  Ming-Hsiu Lee

IPC: G11C16/30 ,  H01L29/788 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11529 ,  G11C11/56 ,  H01L29/423

Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.

公开(公告)号：US20220237405A1

公开(公告)日：2022-07-28

申请号：US17344698

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Yun-Yuan Wang ,  Feng-Min Lee ,  Po-Hao Tseng ,  Ming-Hsiu Lee

IPC: G06K9/62 ,  G06K9/46

Abstract: A data recognition apparatus and a recognition method are provided. The data recognition apparatus includes a data augmentation device, a feature extractor, and a comparator. The data augmentation device receives a plurality of target information and performs augmentation on each of the target information to generate a plurality of augmented target information. The feature extractor receives queried information and the augmented target information to extract features of the augmented target information and the queried information to respectively generate a plurality of augmented target feature values and a queried feature value. The comparator generates a recognition result according to the queried feature value and the augmented target feature values.

公开(公告)号：US20220236951A1

公开(公告)日：2022-07-28

申请号：US17344500

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Po-Hao Tseng ,  Feng-Min Lee ,  Yu-Hsuan Lin

IPC: G06F7/523 ,  G06F7/50 ,  G06F7/02

Abstract: A multiplication and addition operation device and a control method thereof are provided. The multiplication and addition operation device includes a feature information filter and an in-memory calculator. The feature information filter records a plurality of designated bits of a plurality of feature information, compares received input information with the designated bits to generate a comparison result, and generates a selected address according to the comparison result. The in-memory calculator records all bits of the feature information, and generates an operation result by performing a multiplication and addition operation on the feature information and the input information according to the selected address.

公开(公告)号：US20220108748A1

公开(公告)日：2022-04-07

申请号：US17065516

申请日：2020-10-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Po-Hao Tseng ,  Ming-Hsiu Lee ,  Feng-Min Lee

IPC: G11C15/04

Abstract: A ternary content addressable memory and a memory cell thereof are provided. The ternary content addressable memory cell includes a first transistor and a second transistor. The first transistor has a gate to receive a selection signal. A first end of the first transistor is coupled to a match line. A second end of the first transistor is coupled to a source line. The second transistor has a gate to receive an inverted selection signal. A first end of the second transistor is coupled to the match line. A second end of the second transistor is coupled to the source line. The first and second transistors have charge storage structures.