公开(公告)号：US6140191A

公开(公告)日：2000-10-31

申请号：US157973

申请日：1998-09-21

申请人： Mark I. Gardner ,  Mark C. Gilmer ,  Robert Paiz

发明人： Mark I. Gardner ,  Mark C. Gilmer ,  Robert Paiz

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/66575 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/2652 ,  H01L29/66545

摘要： An integrated circuit and a method of making a transistor thereof are provided. The method includes the steps of forming a first stack on the substrate and a second stack on substrate in spaced-apart relation to the first stack, where the first stack has a first layer and first and second spacers adjacent to the first layer and the second stack has a second layer and third and fourth spacers adjacent to the second layer. A gate dielectric layer is formed on the substrate between the first and second stacks and a first conductor layer is formed on the gate dielectric layer. A first source/drain region is formed beneath the first conductor layer and a second source/drain region is formed beneath the second conductor layer. The first and second layers are removed and a first contact is formed on the first source/drain region and a second contact is formed on the second source/drain region. The method integrates gate and source/drain region formation and provides for gate electrodes with work functions tailored for n-channel and p-channel devices.

摘要翻译： 提供集成电路及其制造晶体管的方法。 该方法包括以下步骤：在衬底上形成第一堆叠，并且在衬底上形成与第一堆叠间隔开的第二叠层，其中第一堆叠具有第一层，第一和第二衬垫与第一层相邻， 堆叠具有与第二层相邻的第二层和第三和第四间隔物。 在第一和第二堆叠之间的衬底上形成栅极电介质层，并且在栅极电介质层上形成第一导体层。 第一源极/漏极区域形成在第一导体层下面，并且第二源极/漏极区域形成在第二导体层下面。 去除第一层和第二层，并且在第一源极/漏极区上形成第一接触，并且在第二源极/漏极区上形成第二接触。 该方法集成了栅极和源极/漏极区域形成，为门极提供了针对n沟道和p沟道器件定制的工作功能。

公开(公告)号：US6110784A

公开(公告)日：2000-08-29

申请号：US123673

申请日：1998-07-28

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/51

CPC分类号： H01L21/28185 ,  H01L21/26506 ,  H01L21/28035 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/518 ,  H01L29/6659 ,  H01L21/31604 ,  H01L21/31691

摘要： A transistor and a method of making the same are provided. The transistor includes a substrate that has an upper surface and a gate dielectric layer positioned on the substrate that has a first quantity of nitrogen therein. A gate electrode is positioned on the gate dielectric layer. First and second source/drain regions are positioned in the substrate and laterally separated to define a channel region beneath the gate dielectric layer. The gate dielectric layer may be composed of a high K material with a thin equivalent thickness of oxide, such as TiO.sub.2, Ta.sub.2 O.sub.5, CrO.sub.2 or SrO.sub.2. The nitrogen suppresses later oxide formation which may otherwise increase the equivalent thickness of oxide of the gate dielectric layer. Nitrogen may also be incorporated into the substrate and the gate electrode.

摘要翻译： 提供晶体管及其制造方法。 晶体管包括具有位于基板上的上表面和栅介质层的基板，其中具有第一量的氮。 栅电极位于栅介质层上。 第一和第二源极/漏极区域位于衬底中并且横向分离以限定栅极电介质层下面的沟道区域。 栅介电层可以由具有相当厚度的氧化物如TiO 2，Ta 2 O 5，CrO 2或SrOO的高K材料组成。 氮气抑制后来的氧化物形成，否则可能增加栅极电介质层的氧化物的等效厚度。 氮也可以并入衬底和栅电极中。

公开(公告)号：US6096658A

公开(公告)日：2000-08-01

申请号：US57091

申请日：1998-04-08

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/31116 ,  H01L21/76802

摘要： A process for forming a semiconductor device using a conductive etch stop. The process includes the steps of fabricating a wafer structure up to a first level oxide deposition. A conductive etch stop is deposited over the first level oxide deposition, and selected portions of the conductive etch stop are removed. An inter-level oxide layer is deposited on the conductive etch stop, and selected portions of the inter-level oxide deposition are etched up to the conductive etch stop. The conductive etch stop may be either removed from the semiconductor or left as a conductor.

摘要翻译： 一种使用导电蚀刻停止件形成半导体器件的工艺。 该方法包括制造直到第一级氧化物沉积的晶片结构的步骤。 在第一层氧化物沉积上沉积导电蚀刻停止层，并且去除导电蚀刻停止件的选定部分。 层间氧化物层沉积在导电蚀刻停止点上，层间氧化物沉积的选定部分被蚀刻到导电蚀刻停止点。 导电蚀刻停止件可以从半导体中去除或作为导体留下。

公开(公告)号：US6086976A

公开(公告)日：2000-07-11

申请号：US221351

申请日：1998-12-28

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： B65G49/07 ,  H01L21/68 ,  H01L21/687 ,  B32B3/24

CPC分类号： H01L21/68757 ,  H01L21/68 ,  H01L21/68785 ,  Y10S414/136 ,  Y10T29/41 ,  Y10T428/218 ,  Y10T428/24273 ,  Y10T428/24298

摘要： A semiconductor wafer comprising a single crystalline lattice suitable for use in the manufacture of integrated circuits, namely computer chips and dies, wherein a diameter of the wafer is greater than approximately 150 millimeters and wherein the wafer includes a first hole extending through the wafer. The hole is adapted to facilitate handling of the wafer without directly contacting a surface of the wafer. The wafer preferably includes a primary flat and the first hole includes a flat side having a predetermined and known orientation with respect to the primary flat of the wafer. In one embodiment, the wafer further includes a guide hole formed near the first hole such that the center-points of the first hole and the guide hole are oriented with a predetermined and known orientation with respect to the primary flat of the wafer.

摘要翻译： 一种半导体晶片，其包括适合用于制造集成电路的单晶格，即计算机芯片和裸片，其中晶片的直径大于约150毫米，并且其中晶片包括延伸穿过晶片的第一孔。 该孔适于促进晶片的处理而不直接接触晶片的表面。 晶片优选地包括主平面，并且第一孔包括相对于晶片的初级平面具有预定和已知取向的平坦侧。 在一个实施例中，晶片还包括形成在第一孔附近的引导孔，使得第一孔和引导孔的中心点相对于晶片的主平面以预定和已知的取向定向。

公开(公告)号：US6072213A

公开(公告)日：2000-06-06

申请号：US70393

申请日：1998-04-30

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L21/28123 ,  H01L29/6659

摘要： An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. First and second masks are formed upon a conductive gate layer, wherein the second mask has a second lateral dimension less than a first lateral dimension of the first mask. The second mask is used to pattern a gate conductor from the conductive gate layer such that the gate conductor has an ultra narrow lateral dimension. Lightly doped drain impurity areas are formed self-aligned to sidewall surfaces of the gate conductor. Spacers are formed laterally adjacent the sidewall surfaces of the gate conductor, and source and drain impurity areas are formed self-aligned to sidewall surfaces of the spacers.

摘要翻译： 提供了一种用于形成具有超短沟道长度的晶体管的集成电路制造工艺。 第一和第二掩模形成在导电栅极层上，其中第二掩模具有小于第一掩模的第一横向尺寸的第二横向尺寸。 第二掩模用于从导电栅极层形成栅极导体，使得栅极导体具有超窄的横向尺寸。 轻掺杂漏极杂质区域形成为与栅极导体的侧壁表面自对准。 间隔件横向邻近栅极导体的侧壁表面形成，并且源极和漏极杂质区域形成为自对准到间隔物的侧壁表面。

公开(公告)号：US06060767A

公开(公告)日：2000-05-09

申请号：US183019

申请日：1998-10-30

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/316 ,  H01L21/823864 ,  H01L29/4983 ,  Y10S257/90

摘要： Fluorine bearing spacers on the sidewalls of gate electrodes of a semiconductor device are provided to suppress hot carrier injection in the semiconductor device. In accordance with one embodiment of the invention, a semiconductor device is formed by forming at least one gate electrode on a surface of a substrate and forming fluorine bearing spacers on the sidewalls of the gate electrode. The fluorine bearing spacers may, for example, be formed of an NF.sub.3 -doped glass material.

摘要翻译： 提供半导体器件的栅电极的侧壁上的含氟隔离物以抑制半导体器件中的热载流子注入。 根据本发明的一个实施例，通过在基板的表面上形成至少一个栅电极并在栅电极的侧壁上形成含氟隔离物来形成半导体器件。 含氟隔离物可以例如由掺杂NF 3的玻璃材料形成。

公开(公告)号：US6027992A

公开(公告)日：2000-02-22

申请号：US993455

申请日：1997-12-18

申请人： Mark I. Gardner ,  Mark C. Gilmer

发明人： Mark I. Gardner ,  Mark C. Gilmer

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/3205

CPC分类号： H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/518

摘要： The present invention relates to a process of forming a semiconductor device including forming a gallium and nitrogen bearing layer and forming at least one gate electrode over the gallium and nitrogen bearing barrier layer. The invention also includes a semiconductor device formed according to this process. In another embodiment, the invention includes a semiconductor device including a substrate, a gallium and nitrogen containing barrier layer disposed over the substrate, and at least one gate electrode disposed over the gallium and nitrogen bearing barrier layer.

摘要翻译： 本发明涉及一种形成半导体器件的方法，该半导体器件包括形成含镓和氮的承载层并在含氮和氮的阻挡层上形成至少一个栅电极。 本发明还包括根据该方法形成的半导体器件。 在另一个实施例中，本发明包括一种包括衬底，设置在衬底上的含镓和氮的阻挡层的半导体器件，以及设置在含氮和氮的阻挡层之上的至少一个栅电极。

公开(公告)号：US5998270A

公开(公告)日：1999-12-07

申请号：US856545

申请日：1997-05-15

申请人： Mark C. Gilmer ,  Mark I. Gardner

发明人： Mark C. Gilmer ,  Mark I. Gardner

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L21/28017

摘要： A semiconductor device fabrication process in which an oxynitride layer and a polysilicon layer are formed in the same reaction chamber is provided. In accordance with one embodiment of the invention, a semiconductor device is formed by forming, in a reaction chamber, an oxynitride layer on a surface of a substrate and forming, in the same reaction chamber, a polysilicon layer over the oxynitride layer. The oxynitride layer may be used to form a gate oxide and the polysilicon layer used to form a gate electrode.

摘要翻译： 提供了在相同的反应室中形成氧氮化物层和多晶硅层的半导体器件制造工艺。 根据本发明的一个实施例，半导体器件通过在反应室中形成在衬底的表面上的氧氮化物层并在相同的反应室中在氮氧化物层上形成多晶硅层来形成半导体器件。 氧氮化物层可用于形成栅极氧化物和用于形成栅电极的多晶硅层。

公开(公告)号：US5907780A

公开(公告)日：1999-05-25

申请号：US98704

申请日：1998-06-17

申请人： Mark C. Gilmer ,  Mark I. Gardner

发明人： Mark C. Gilmer ,  Mark I. Gardner

IPC分类号： H01L21/28 ,  H01L21/3115 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28185 ,  H01L21/28158 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/66825 ,  H01J2237/0812 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/7833

摘要： An integrated circuit fabrication process is provided for forming silicon dioxide in the vacancies of a gate dielectric comprising metal oxide. The gate dielectric has a relatively high dielectric constant to promote high capacitive coupling between two conductive layers separated by the gate dielectric. The gate dielectric may be used in, e.g., a MOS transistor device or an EEPROM memory cell. The silicon dioxide is formed within the gate dielectric by first incorporating silicon atoms within the gate dielectric using gas cluster ion beam implantation. Gas cluster ion beam implantation affords shallow implantation of the silicon atoms. The gate dielectric is then annealed in a diffusion furnace while being exposed to a steam- or oxygen-bearing ambient. As a result of being heated, Si atoms react with O atoms to form SiO.sub.2 which fills oxygen vacancies in the gate dielectric. Absent the oxygen vacancies, the gate dielectric is less likely to allow current to leak between the two conductive layers. The SiO.sub.2 serves to terminate dangling bonds within the gate dielectric so that hot carriers and foreign species are substantially inhibited from being trapped within the gate dielectric.

摘要翻译： 提供了一种用于在包含金属氧化物的栅极电介质的空位中形成二氧化硅的集成电路制造工艺。 栅极电介质具有相对高的介电常数，以促进由栅极电介质隔开的两个导电层之间的高电容耦合。 栅极电介质可以用在例如MOS晶体管器件或EEPROM存储器单元中。 通过首先使用气体簇离子束注入在栅极电介质中并入硅原子，在栅极电介质内形成二氧化硅。 气体簇离子束注入提供了硅原子的浅注入。 然后将栅极电介质在扩散炉中退火，同时暴露于蒸汽或含氧环境。 作为加热的结果，Si原子与O原子反应形成填充栅极电介质中的氧空位的SiO 2。 缺少氧空位，栅电介质不太可能允许电流在两个导电层之间泄漏。 SiO 2用于终止栅极电介质内的悬挂键，使得热载流子和外来物质基本上被禁止被捕获在栅极电介质内。

公开(公告)号：US5904542A

公开(公告)日：1999-05-18

申请号：US825015

申请日：1997-03-26

申请人： Mark C. Gilmer ,  Mark I. Gardner ,  Thomas E. Spikes

发明人： Mark C. Gilmer ,  Mark I. Gardner ,  Thomas E. Spikes

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202 ,  Y10S438/913

摘要： An in situ process is provided for isolating semiconductor devices according to a LOCOS process. The invention contemplates performing field oxide growth, nitride layer removal, sacrificial oxide growth and removal, and gate oxide growth all within a single chamber without removing the wafers from the chamber during processing. The invention is believed to result in increased yields and process throughput by reducing the exposure of the wafers to outer-chamber contaminants, thermal stress, and transportation damage, as well as reducing inter-chamber transportation time. The invention also contemplates an in situ processing chamber adapted for performing field oxide growth, nitride layer removal, sacrificial oxide growth and removal, and gate oxide growth as part of a LOCOS isolation process. The in situ processing chamber is adapted for thermal oxidation and etching processes to implement the LOCOS isolation structure. A conventional oxidation furnace may be adapted to provide the in situ processing chamber by adapting the oxidation furnace to accept etchant gasses. Other conventional chambers or a specialized chamber may also be adapted according to the present invention for the in situ LOCOS process.

摘要翻译： 提供了根据LOCOS工艺隔离半导体器件的原位工艺。 本发明设想在处理期间不在单元室内执行场氧化物生长，氮化物层去除，牺牲氧化物生长和去除以及栅极氧化物生长，而不从室中移除晶片。 据信本发明通过减少晶片暴露于外室污染物，热应力和运输损伤以及减少室间运输时间而导致产量和工艺生产量的提高。 本发明还考虑了适于执行场氧化物生长，氮化物层去除，牺牲氧化物生长和去除以及作为LOCOS隔离工艺的一部分的栅极氧化物生长的原位处理室。 原位处理室适用于热氧化和蚀刻工艺，以实现LOCOS隔离结构。 常规的氧化炉可适于通过使氧化炉适应接受腐蚀气体来提供原位处理室。 根据本发明，其他常规腔室或专用腔室也可以适用于原位LOCOS过程。