公开(公告)号：US20110102116A1

公开(公告)日：2011-05-05

申请号：US12611294

申请日：2009-11-03

Applicant: Robert G. Biskeborn ,  Philipp Herget ,  Bucknell C. Webb

Inventor： Robert G. Biskeborn ,  Philipp Herget ,  Bucknell C. Webb

IPC: H01F7/02

CPC classification number: G11B5/3116 ,  G11B5/17 ,  G11B5/23 ,  G11B5/265 ,  G11B5/2652 ,  G11B5/59638

Abstract: A magnetic device according to one embodiment includes a source of flux; a magnetic pole coupled to the source of flux, the magnetic pole having two or more gaps; and a low reluctance path positioned towards at least one of the gaps and not positioned towards at least one other of the gaps for affecting a magnetic field formed at the at least one of the gaps when the source of flux is generating flux. Other disclosed embodiments include devices having coil turns with a non-uniform placement in the magnetic yoke for altering a magnetic field formed at the at least one of the gaps during writing. In further embodiments, a geometry of the magnetic pole near or at one of the gaps is different than a geometry of the magnetic pole near or at another of the gaps to help equalize fields formed at the gaps when the source of flux is generating flux.

Abstract translation: 根据一个实施例的磁性装置包括通量源; 耦合到磁通源的磁极，所述磁极具有两个或更多个间隙; 以及朝向所述间隙中的至少一个定位的低磁阻路径，并且朝向所述间隙中的至少另一个定位，以在所述通量源产生磁通时影响形成在所述至少一个间隙处的磁场。 其他公开的实施例包括具有在磁轭中具有不均匀布置的线圈匝的装置，用于在写入期间改变在至少一个间隙处形成的磁场。 在另外的实施例中，靠近或在其中一个间隙处的磁极的几何形状不同于磁极在靠近或另一个间隙处的几何形状，以帮助当磁通源产生磁通时在间隙处形成的场均衡。

公开(公告)号：US07936060B2

公开(公告)日：2011-05-03

申请号：US12431827

申请日：2009-04-29

Applicant: Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

Inventor： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

IPC: H01L23/52

CPC classification number: H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

Abstract translation: 提供一种电子器件组件，其包括衬底，插入器和集成电路芯片。 衬底由具有第一热膨胀性的第一材料制成，并且插入器和集成电路芯片由具有第二热膨胀性的第二材料制成。 第二热膨胀性与第一热膨胀性不同，因此在衬底和插入件或芯片之间存在热膨胀失配系数。 插入器经由第一多个电触点和底部填充粘合剂耦合到基板，所述底部填充粘合剂至少部分地围绕电触点以将插入件结合到基板，从而减少第一多个电触点上的应变。 集成电路芯片仅通过第二多个电触点而耦合到插入器，而不使用围绕第二多个电触点的粘合剂。

公开(公告)号：US07741722B2

公开(公告)日：2010-06-22

申请号：US11690181

申请日：2007-03-23

Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

Abstract translation: 一种晶片通孔结构及其形成方法。 贯通晶片通孔结构包括具有开口和顶部晶片表面的晶片。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 贯通晶片通孔结构还包括在开口中的通晶片通孔。 贯通晶片通孔具有矩形板的形状。 贯通晶片通孔在第一参考方向上的高度基本上等于晶片在第一参考方向上的厚度。 贯穿晶片通孔在第二参考方向上的长度比通过晶片通孔在第三参考方向上的宽度大至少十倍。 第一，第二和第三参考方向彼此垂直。

公开(公告)号：US20080274583A1

公开(公告)日：2008-11-06

申请号：US11690181

申请日：2007-03-23

Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

IPC: H01L21/00

CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

Abstract translation: 一种晶片通孔结构及其形成方法。 贯通晶片通孔结构包括具有开口和顶部晶片表面的晶片。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 贯通晶片通孔结构还包括在开口中的通晶片通孔。 贯通晶片通孔具有矩形板的形状。 贯通晶片通孔在第一参考方向上的高度基本上等于晶片在第一参考方向上的厚度。 贯穿晶片通孔在第二参考方向上的长度比通过晶片通孔在第三参考方向上的宽度大至少十倍。 第一，第二和第三参考方向彼此垂直。

公开(公告)号：US07345353B2

公开(公告)日：2008-03-18

申请号：US11323568

申请日：2005-12-30

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01L23/58

CPC classification number: H01L21/481 ,  H01L23/13 ,  H01L23/147 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/81 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15159 ,  H01L2924/3511 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An apparatus and method providing flexibility to a silicon chip carrier which, in at least one embodiment, comprises multiple chips and a silicon chip carrier having thinned regions between some adjacent chips, thus, allowing for increased flexibility and reduced package warpage.

Abstract translation: 一种为硅芯片载体提供灵活性的装置和方法，该芯片载体在至少一个实施例中包括多个芯片，以及在一些相邻芯片之间具有薄化区域的硅芯片载体，从而允许增加灵活性并减少封装翘曲。

公开(公告)号：US5907447A

公开(公告)日：1999-05-25

申请号：US893316

申请日：1997-07-16

Applicant: Edward John Yarmchuk ,  Mark Delorman Schultz ,  Bucknell C. Webb ,  Timothy Joseph Chainer

Inventor： Edward John Yarmchuk ,  Mark Delorman Schultz ,  Bucknell C. Webb ,  Timothy Joseph Chainer

IPC: G11B5/596 ,  G11B21/10 ,  G11B5/012

CPC classification number: G11B21/106 ,  G11B21/10 ,  G11B5/59633 ,  G11B5/59644

Abstract: A mechanism for servowriting on a storage medium of a storage device. The storage device has a transducer and a servo loop for positioning the transducer with respect to the storage medium. At least one transition is written on a track of the storage medium, while servoing on other transitions previously recorded on the storage medium. A reference waveform is derived as a function of a closed loop response of the servo loop and a position error waveform. The position error waveform corresponds to one or more position errors of the transducer relative to the previously recorded transitions. The reference waveform is usable in writing subsequent tracks on the storage medium. Using the reference waveform for writing subsequent tracks provides a substantial rejection of mechanical disturbances by the servo loop.

Abstract translation: 一种用于在存储设备的存储介质上进行伺服驱动的机制。 存储装置具有用于相对于存储介质定位换能器的换能器和伺服回路。 至少一个转换被写在存储介质的轨道上，同时伺服在先前记录在存储介质上的其它转换。 作为伺服环路的闭环响应和位置误差波形的函数导出参考波形。 位置误差波形对应于传感器相对于先前记录的转换的一个或多个位置误差。 参考波形可用于将后续轨道写入存储介质上。 使用参考波形写入后续轨道可以显着抑制伺服回路的机械扰动。

公开(公告)号：US5142426A

公开(公告)日：1992-08-25

申请号：US542288

申请日：1990-06-21

Applicant: Mark E. Re ,  Michael A. Russak ,  Bucknell C. Webb

Inventor： Mark E. Re ,  Michael A. Russak ,  Bucknell C. Webb

IPC: G11B5/33 ,  G11B5/31

CPC classification number: G11B5/3143

Abstract: A thin film magnetic head, having a predetermined cut-off frequency is constructed of alternating first and second layers, the first layers include a magnetic material and the second layers include a resistive material. The resistivity of the second layers is chosen so that the head's cut-off frequency exceeds the head's required frequency response. The resistivity of the second layers is chosen to be considerably less than any level of resistivity which falls within the insulation regime.