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51.发明申请GROUP III-N TRANSISTORS FOR SYSTEM ON CHIP (SOC) ARCHITECTURE INTEGRATING POWER MANAGEMENT AND RADIO FREQUENCY CIRCUITS 审中-公开用于芯片（SOC）系统的组III-N晶体管集成电源管理和无线电频率电路公开(公告)号：US20130271208A1
公开(公告)日：2013-10-17
申请号：US13977195
申请日：2011-12-19
申请人： Han Wui Then , Robert Chau , Valluri Rao , Niloy Mukherjee , Marko Radosavljevic , Ravi Pillarisetty , Gilbert Dewey , Jack Kavalieros
发明人： Han Wui Then , Robert Chau , Valluri Rao , Niloy Mukherjee , Marko Radosavljevic , Ravi Pillarisetty , Gilbert Dewey , Jack Kavalieros
CPC分类号： H01L25/072 , H01L21/8252 , H01L21/8258 , H01L25/50 , H01L27/0605 , H01L27/088 , H01L29/2003 , H01L29/4236 , H01L29/66462 , H01L29/7783 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.
摘要翻译： 片上系统（SoC）解决方案使用基于能够实现高Ft和足够高击穿电压（BV）的III类氮化物（III-N）的晶体管技术将RFIC与PMIC集成，以实现高电压和/ 或高功率电路。 在实施例中，III-N晶体管架构适于缩放以维持许多连续器件世代的性能改进的轨迹。 在实施例中，III-N晶体管架构适于与IV类晶体管架构（诸如平面和非平面硅CMOS晶体管技术）的单片集成。 具有凹入栅极，对称源极和漏极，再生长源极/漏极中的一个或多个的平面和非平面HEMT实施例使用允许增强模式操作和良好栅极钝化的替代栅极技术形成。
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公开(公告)号：US20110312140A1
公开(公告)日：2011-12-22
申请号：US13216569
申请日：2011-08-24
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/0657 , H01L29/0834 , H01L29/42312 , H01L29/66356 , H01L29/7391
摘要： A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.
摘要翻译： 微电子器件包括具有第一栅极和第二栅极的P-I-N（p +区域，本征半导体和n +区域）半导体。 第一栅极是设置在上表面平面上的栅极堆叠，并且第二栅极从超出第一平面的第二平面访问半导体本体。
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53.发明授权公开(公告)号：US07915642B2
公开(公告)日：2011-03-29
申请号：US12319097
申请日：2008-12-30
申请人： Ravi Pillarisetty , Mantu Hudait , Marko Radosavljevic , Willy Rachmady , Gilbert Dewey , Jack Kavalieros
发明人： Ravi Pillarisetty , Mantu Hudait , Marko Radosavljevic , Willy Rachmady , Gilbert Dewey , Jack Kavalieros
IPC分类号： H01L29/778
CPC分类号： H01L29/155 , H01L21/823807 , H01L21/823892 , H01L29/0653 , H01L29/205 , H01L29/207 , H01L29/66431 , H01L29/66462 , H01L29/66795 , H01L29/7831
摘要： Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.
摘要翻译： 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例。
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公开(公告)号：US20130277683A1
公开(公告)日：2013-10-24
申请号：US13976837
申请日：2011-12-19
申请人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
发明人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/7787 , G06F1/1633 , G06F1/189 , H01L21/02381 , H01L21/02433 , H01L21/0254 , H01L29/045 , H01L29/0657 , H01L29/0847 , H01L29/1037 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/66462 , H01L29/7783 , H01L29/7786 , H01L29/7789 , H01L29/785 , H03F3/195 , H03F3/213 , H03F2200/451
摘要： Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (10 10) plane on a (110) plane of the silicon.
摘要翻译： 用于高压和高频工作的晶体管。 具有设置在第一和第二相对侧壁之间的顶表面的非平面极性结晶半导体本体包括具有设置在第一和第二侧壁上的第一晶体半导体层的沟道区。 第一晶体半导体层是在沟道区内提供二维电子气（2DEG）。 栅极结构沿至少第二侧壁设置在第一晶体半导体层上方，以调制2DEG。 非平面极性结晶半导体主体的第一和第二侧壁可具有不同的极性，其中通道靠近第一侧壁。 栅极结构可以沿着侧壁中的第二侧面以栅极背栅。 极性结晶半导体体可以是在硅衬底上形成的III族氮化物，其中（10 10）面在硅的（110）平面上。
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55.发明申请公开(公告)号：US20130270512A1
公开(公告)日：2013-10-17
申请号：US13976411
申请日：2011-12-19
申请人： Marko Radosavljevic , Ravi Pillarisetty , Gilbert Dewey , Niloy Mukherjee , Jack Kavalieros , Willy Rachmady , Van Le , Benjamin Chu-Kung , Matthew Metz , Robert Chau
发明人： Marko Radosavljevic , Ravi Pillarisetty , Gilbert Dewey , Niloy Mukherjee , Jack Kavalieros , Willy Rachmady , Van Le , Benjamin Chu-Kung , Matthew Metz , Robert Chau
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/845 , B82Y10/00 , H01L21/0228 , H01L21/02532 , H01L21/02546 , H01L21/30604 , H01L21/823807 , H01L21/823821 , H01L21/8258 , H01L27/092 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/0673 , H01L29/16 , H01L29/20 , H01L29/205 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/775 , H01L29/785 , H01L29/7853 , H01L29/78696
摘要： Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
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56.发明申请公开(公告)号：US20100163927A1
公开(公告)日：2010-07-01
申请号：US12319097
申请日：2008-12-30
申请人： Ravi Pillarisetty , Mantu Hudait , Marko Radosavljevic , Willy Rachmady , Gilbert Dewey , Jack Kavalieros
发明人： Ravi Pillarisetty , Mantu Hudait , Marko Radosavljevic , Willy Rachmady , Gilbert Dewey , Jack Kavalieros
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/155 , H01L21/823807 , H01L21/823892 , H01L29/0653 , H01L29/205 , H01L29/207 , H01L29/66431 , H01L29/66462 , H01L29/66795 , H01L29/7831
摘要： Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.
摘要翻译： 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例。
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公开(公告)号：US09240410B2
公开(公告)日：2016-01-19
申请号：US13976413
申请日：2011-12-19
申请人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
发明人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
IPC分类号： H01L27/088 , H01L29/66 , H01L29/775 , H01L29/778 , H01L29/786 , H01L29/78 , B82Y10/00 , H01L29/06 , H01L29/20
CPC分类号： H01L29/158 , B82Y10/00 , H01L21/02603 , H01L23/66 , H01L27/0605 , H01L27/0886 , H01L29/045 , H01L29/0669 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/2003 , H01L29/205 , H01L29/42392 , H01L29/66431 , H01L29/66462 , H01L29/66469 , H01L29/66522 , H01L29/66742 , H01L29/775 , H01L29/778 , H01L29/7786 , H01L29/785 , H01L29/78618 , H01L29/78681 , H01L29/78696 , H01L2223/6677 , Y10S977/938
摘要： A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.
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公开(公告)号：US20130279145A1
公开(公告)日：2013-10-24
申请号：US13976413
申请日：2011-12-19
申请人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
发明人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/158 , B82Y10/00 , H01L21/02603 , H01L23/66 , H01L27/0605 , H01L27/0886 , H01L29/045 , H01L29/0669 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/2003 , H01L29/205 , H01L29/42392 , H01L29/66431 , H01L29/66462 , H01L29/66469 , H01L29/66522 , H01L29/66742 , H01L29/775 , H01L29/778 , H01L29/7786 , H01L29/785 , H01L29/78618 , H01L29/78681 , H01L29/78696 , H01L2223/6677 , Y10S977/938
摘要： A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.
摘要翻译： III-N族纳米线设置在基板上。 纳米线的纵向长度被限定为第一组III-N材料的沟道区域，与沟道区域的第一端电耦合的源极区域和与沟道区域的第二端电耦合的漏极区域。 第一组III-N材料上的第二组III-N材料用作纳米线表面上的电荷诱导层和/或阻挡层。 栅极绝缘体和/或栅极导体在通道区域内的纳米线周围同轴地包裹。 排水和源极接触件可以类似地同轴地围绕漏极和源极区域包裹。
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59.发明申请公开(公告)号：US20100327317A1
公开(公告)日：2010-12-30
申请号：US12459262
申请日：2009-06-26
IPC分类号： H01L29/12 , H01L29/772 , H01L21/336
CPC分类号： H01L29/78684 , H01L29/78603
摘要： Embodiments of an apparatus and methods for providing germanium on insulator using a large bandgap barrier layer are generally described herein. Other embodiments may be described and claimed.
摘要翻译： 在此通常描述使用大带隙阻挡层在绝缘体上提供锗的装置和方法的实施例。 可以描述和要求保护其他实施例。
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60.发明授权公开(公告)号：US09653559B2
公开(公告)日：2017-05-16
申请号：US13997166
申请日：2011-12-27
申请人： Niloy Mukherjee , Gilbert Dewey , Marko Radosavljevic , Niti Goel , Sanaz Kabehie , Matthew V. Metz , Robert S. Chau
发明人： Niloy Mukherjee , Gilbert Dewey , Marko Radosavljevic , Niti Goel , Sanaz Kabehie , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L29/417 , H01L29/40 , H01L21/225 , H01L29/66 , H01L21/768 , H01L21/223 , H01L21/265
CPC分类号： H01L29/41725 , H01L21/2236 , H01L21/2254 , H01L21/26513 , H01L21/76814 , H01L29/401 , H01L29/41783 , H01L29/66628
摘要： A die includes a semiconductive prominence and a surface-doped structure on the prominence. The surface-doped structure makes contact with contact metallization. The prominence may be a source- or drain contact for a transistor. Processes of making the surface-doped structure include wet-vapor- and implantation techniques, and include annealing techniques to drive in the surface doping to only near-surface depths in the semiconductive prominence.
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