公开(公告)号：US09318336B2

公开(公告)日：2016-04-19

申请号：US13326767

申请日：2011-12-15

申请人： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

发明人： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/49

CPC分类号： H01L21/28273 ,  H01L21/0228 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/11546 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7881

摘要： A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.

公开(公告)号：US08759172B2

公开(公告)日：2014-06-24

申请号：US13449433

申请日：2012-04-18

申请人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

发明人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

IPC分类号： H01L21/336

CPC分类号： H01L29/517 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/66545

摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。 栅极电介质盖形成在金属栅极导体上。 栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。 接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

公开(公告)号：US20130277764A1

公开(公告)日：2013-10-24

申请号：US13449433

申请日：2012-04-18

申请人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

发明人： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/66545

摘要： A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

摘要翻译： 一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。 栅极电介质盖形成在金属栅极导体上。 栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。 接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

公开(公告)号：US08518766B2

公开(公告)日：2013-08-27

申请号：US13536366

申请日：2012-06-28

申请人： Nestor A. Bojarczuk ,  Michael P. Chudzik ,  Matthew W. Copel ,  Supratik Guha ,  Richard A. Haight ,  Vijay Narayanan ,  Martin P. O'Boyle ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk ,  Michael P. Chudzik ,  Matthew W. Copel ,  Supratik Guha ,  Richard A. Haight ,  Vijay Narayanan ,  Martin P. O'Boyle ,  Vamsi K. Paruchuri

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/70

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/51

摘要： A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.

摘要翻译： 场效应晶体管（FET）包括至少部分地设置在身体区域中的体区和源区。 FET还包括至少部分地设置在体区中的漏极区域和氮氧化钼（MoNO）栅极。 FET还包括具有高介电常数（k）的电介质，其布置在体区和MoNO门之间。

公开(公告)号：US08507992B2

公开(公告)日：2013-08-13

申请号：US13048170

申请日：2011-03-15

申请人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

发明人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

IPC分类号： H01L21/70

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.

摘要翻译： 提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

公开(公告)号：US20120286374A1

公开(公告)日：2012-11-15

申请号：US13556795

申请日：2012-07-24

申请人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

发明人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  William K. Henson ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Naim Moumen ,  Wesley C. Natzle

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L21/28088 ,  H01L21/2822 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66575

摘要： Methods for fabricating gate electrode/high-k dielectric gate structures having an improved resistance to the growth of silicon dioxide (oxide) at the dielectric/silicon-based substrate interface. In an embodiment, a method of forming a transistor gate structure comprises: incorporating nitrogen into a silicon-based substrate proximate a surface of the substrate; depositing a high-k gate dielectric across the silicon-based substrate; and depositing a gate electrode across the high-k dielectric to form the gate structure. In one embodiment, the gate electrode comprises titanium nitride rich in titanium for inhibiting diffusion of oxygen.

摘要翻译： 用于制造栅电极/高k电介质栅极结构的方法，其具有改善的耐电介质/硅基衬底界面处二氧化硅（氧化物）生长的能力。 在一个实施例中，形成晶体管栅极结构的方法包括：将氮掺入靠近衬底表面的硅基衬底中; 在所述硅基衬底上沉积高k栅极电介质; 以及在高k电介质上沉积栅电极以形成栅极结构。 在一个实施例中，栅电极包含富含钛的氮化钛以抑制氧的扩散。

公开(公告)号：US08227870B2

公开(公告)日：2012-07-24

申请号：US13364564

申请日：2012-02-02

申请人： Michael P. Chudzik ,  Ricardo A. Donaton ,  William K. Henson ,  Yue Liang

发明人： Michael P. Chudzik ,  Ricardo A. Donaton ,  William K. Henson ,  Yue Liang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823437 ,  H01L21/28088 ,  H01L27/0629 ,  H01L27/0802 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

摘要： A method and structure to scale metal gate height in high-k/metal gate transistors. A method includes forming a dummy gate and at least one polysilicon feature, all of which are formed from a same polysilicon layer and wherein the dummy gate is formed over a gate metal layer associated with a transistor. The method also includes selectively removing the dummy gate while protecting the at least one polysilicon feature. The method further includes forming a gate contact on the gate metal layer to thereby form a metal gate having a height that is less than half a height of the at least one polysilicon feature.

公开(公告)号：US20120181631A1

公开(公告)日：2012-07-19

申请号：US13431328

申请日：2012-03-27

申请人： Stephen W. Bedell ,  Ashima B. Chakravarti ,  Michael P. Chudzik ,  Judson R. Holt ,  Dominic J. Schepis

发明人： Stephen W. Bedell ,  Ashima B. Chakravarti ,  Michael P. Chudzik ,  Judson R. Holt ,  Dominic J. Schepis

IPC分类号： H01L29/78

CPC分类号： H01L29/1054 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02612 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.

摘要翻译： 公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。 在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄 被提供。

公开(公告)号：US20120108017A1

公开(公告)日：2012-05-03

申请号：US13347014

申请日：2012-01-10

申请人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

发明人： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

IPC分类号： H01L21/782 ,  H01L21/8238

CPC分类号： H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

摘要： Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

摘要翻译： 在掺杂半导体阱上形成多种类型的栅叠层。 在掺杂半导体阱上形成高介电常数（高k）栅极电介质。 在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。 在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。 然后在阈值电压调整氧化物层上形成导电栅极材料层。 一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。 其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。 具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

公开(公告)号：US20110248350A1

公开(公告)日：2011-10-13

申请号：US12757323

申请日：2010-04-09

申请人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

发明人： Michael P. Chudzik ,  William K. Henson ,  Unoh Kwon

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L21/28176 ,  H01L21/28079 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/517 ,  H01L29/6659

摘要： Adjustment of a switching threshold of a field effect transistor including a gate structure including a Hi-K gate dielectric and a metal gate is achieved and switching thresholds coordinated between NFETs and PFETs by providing fixed charge materials in a thin interfacial layer adjacent to the conduction channel of the transistor that is provided for adhesion of the Hi-K material, preferably hafnium oxide or HfSiON, depending on design, to semiconductor material rather than diffusing fixed charge material into the Hi-K material after it has been applied. The greater proximity of the fixed charge material to the conduction channel of the transistor increases the effectiveness of fixed charge material to adjust the threshold due to the work function of the metal gate, particularly where the same metal or alloy is used for both NFETs and PFETs in an integrated circuit; preventing the thresholds from being properly coordinated.

摘要翻译： 实现了包括包括Hi-K栅极电介质和金属栅极的栅极结构的场效应晶体管的开关阈值的调整，并且通过在与导电沟道相邻的薄界面层中提供固定的电荷材料来在NFET和PFET之间协调切换阈值 根据设计将Hi-K材料，优选氧化铪或HfSiON粘附到半导体材料上而不是将固定的电荷材料扩散到Hi-K材料中之后施加的晶体管。 固定电荷材料与晶体管的导通通道的接近程度增加了由于金属栅极的功函数而导致的固定电荷材料的调整阈值的有效性，特别是当相同的金属或合金用于NFET和PFET时 在集成电路中; 防止阈值正确协调。