公开(公告)号：US11791212B2

公开(公告)日：2023-10-17

申请号：US16713309

申请日：2019-12-13

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L21/78 ,  H01L21/50 ,  H01L21/683 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01L21/50 ,  H01L21/67051 ,  H01L21/6836 ,  H01L21/6708 ,  H01L2221/68322 ,  H01L2221/68327

Abstract: Methods for releasing thinned semiconductor dies from a mount tape and associated apparatuses are disclosed. In one embodiment, a sacrificial layer may be disposed at a back side of thinned substrate including semiconductor dies. The sacrificial layer includes materials soluble in contact with a fluid (and/or vapor). A sheet of perforated mount tape may be attached to the sacrificial layer and an ejection component may be provided under a target semiconductor die to be released. The ejection component is configured to create a locally confined puddle of the fluid under the target semiconductor die such that the sacrificial layer is removed to release the target semiconductor die from the mount tape. Further, a support component may be provided to pick up the target semiconductor die after the target semiconductor die is released from the mount tape.

公开(公告)号：US11776908B2

公开(公告)日：2023-10-03

申请号：US17231210

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L23/48 ,  H01L23/532 ,  H01L25/00 ,  H01L23/31 ,  H01L21/78 ,  H01L25/065

CPC classification number: H01L23/53238 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50

Abstract: Semiconductor dies with edges protected and methods for generating the semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, trenches are formed on a front side of a substrate including semiconductor dies. Individual trenches correspond to scribe lines of the substrate where each trench has a depth greater than a final thickness of the semiconductor dies. A composite layer may be formed on sidewalls of the trenches to protect the edges of the semiconductor dies. The composite layer includes a metallic layer that shields the semiconductor dies from electromagnetic interference. Subsequently, the substrate may be thinned from a back side to singulate individual semiconductor dies from the substrate.

公开(公告)号：US11670612B2

公开(公告)日：2023-06-06

申请号：US17176095

申请日：2021-02-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Benjamin L. McClain ,  Jeremy E. Minnich ,  Zhaohui Ma

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/033 ,  H01L21/60

CPC classification number: H01L24/17 ,  H01L21/0337 ,  H01L24/14 ,  H01L24/81 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2021/60007 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2224/92125 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device assembly that includes a semiconductor device positioned over a substrate with a number of electrical interconnections formed between the semiconductor device and the substrate. The surface of the substrate includes a plurality of discrete solder mask standoffs that extend towards the semiconductor device. A thermal compression bonding process is used to melt solder to form the electrical interconnects, which lowers the semiconductor device to contact and be supported by the plurality of discrete solder mask standoffs. The solder mask standoffs permit the application of a higher pressure during the bonding process than using traditional solder masks. The solder mask standoffs may have various polygonal or non-polygonal shapes and may be positioned in pattern to protect sensitive areas of the semiconductor device and/or the substrate. The solder mask standoffs may be an elongated shape that protects areas of the semiconductor device and/or substrate.

公开(公告)号：US20220375893A1

公开(公告)日：2022-11-24

申请号：US17817803

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065

Abstract: This patent application relates to methods and apparatus for temperature modification within a stack of microelectronic devices for mutual collective bonding of the microelectronic devices, and to related substrates and assemblies.

公开(公告)号：US11410964B2

公开(公告)日：2022-08-09

申请号：US16693192

申请日：2019-11-22

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaekyu Song ,  Sui Chi Huang

IPC: H01L21/67 ,  H01L21/50 ,  H01L23/00 ,  H01L21/60

Abstract: Systems and methods for controlling contamination during thermocompression bonding are provided herein. The tool generally includes a bondhead having a first channel extending in a lateral direction from a first port along a second side toward a perimeter of the bondhead. In several examples, the bondhead includes a second channel fluidly coupled to a second port and extending in a lateral direction along an inset surface of the bondhead, where the second channel at least partially surrounds the first channel. In other examples, the tool includes a vacuum manifold having a vacuum opening positioned laterally outward from the bondhead. A first flow unit is coupled to the first channel and is configured to withdraw air. A second flow unit is coupled to the second port or the manifold to withdraw fluid and prevent outgas sing bonding materials from entering the first channel, depositing on the bondhead, and/or contaminating neighboring semiconductor components.

公开(公告)号：US20220013401A1

公开(公告)日：2022-01-13

申请号：US16923754

申请日：2020-07-08

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L21/683 ,  H01L23/48 ,  H01L21/48

Abstract: Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.

公开(公告)号：US11189590B2

公开(公告)日：2021-11-30

申请号：US16715594

申请日：2019-12-16

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/00 ,  H01L21/78 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/29

Abstract: Processes for adjusting dimensions of dielectric bond line materials in stacks of microelectronic components to prevent extrusion of the dielectric bond line materials beyond component peripheries during thermocompression bonding by patterning the materials with boundary portions inset from component peripheries, or employing an inset dielectric material surrounded by another solidified dielectric material. Related material films, articles and assemblies are also disclosed.

公开(公告)号：US20210233887A1

公开(公告)日：2021-07-29

申请号：US17301843

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Benjamin L. McClain ,  Brandon P. Wirz ,  Zhaohui Ma

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.

公开(公告)号：US20210159206A1

公开(公告)日：2021-05-27

申请号：US16693192

申请日：2019-11-22

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaekyu Song ,  Sui Chi Huang

IPC: H01L23/00 ,  H01L21/67 ,  H01L21/50

Abstract: Systems and methods for controlling contamination during thermocompression bonding are provided herein. The tool generally includes a bondhead having a first channel extending in a lateral direction from a first port along a second side toward a perimeter of the bondhead. In several examples, the bondhead includes a second channel fluidly coupled to a second port and extending in a lateral direction along an inset surface of the bondhead, where the second channel at least partially surrounds the first channel. In other examples, the tool includes a vacuum manifold having a vacuum opening positioned laterally outward from the bondhead. A first flow unit is coupled to the first channel and is configured to withdraw air. A second flow unit is coupled to the second port or the manifold to withdraw fluid and prevent outgas sing bonding materials from entering the first channel, depositing on the bondhead, and/or contaminating neighboring semiconductor components.

公开(公告)号：US11004828B2

公开(公告)日：2021-05-11

申请号：US16553504

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Bradley R. Bitz ,  Pei Sian Shao

IPC: H01L21/00 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  B29C43/18 ,  B29C43/36 ,  B29L31/34 ,  B29K63/00

Abstract: Methods for fabricating microelectronic device assemblies, the method comprising providing mutually spaced stacks of microelectronic devices on a substrate and substantially concurrently encapsulating the stacks of microelectronic devices on the substrate and gang bonding mutually aligned conductive elements of vertically adjacent microelectronic devices. Compression molding apparatus for implementing the methods, and resulting microelectronic device assemblies are also disclosed.