公开(公告)号：US10256275B2

公开(公告)日：2019-04-09

申请号：US14594813

申请日：2015-01-12

Applicant: Micron Technology, Inc.

Inventor： Zengtao T. Liu

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the source/drain regions of one of the select transistors. The local second vertical line is in conductive connection with the other source/drain region of the one select transistor. Individual memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed.

公开(公告)号：US10241185B2

公开(公告)日：2019-03-26

申请号：US15996733

申请日：2018-06-04

Applicant: Micron Technology, Inc.

Inventor： Zengtao T. Liu

IPC: G11C11/00 ,  G01R33/58 ,  G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  G11C13/00 ,  G11C7/10 ,  H01L27/24 ,  H01L45/00 ,  G01R33/12 ,  G01R33/24

Abstract: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.

公开(公告)号：US09679642B2

公开(公告)日：2017-06-13

申请号：US14739798

申请日：2015-06-15

Applicant: Micron Technology, Inc.

Inventor： Zengtao T. Liu ,  Kirk D. Prall

IPC: G11C13/00 ,  G11C8/08

CPC classification number: G11C13/004 ,  G11C8/08 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0038 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2013/0083 ,  G11C2213/77

Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

公开(公告)号：US09548335B2

公开(公告)日：2017-01-17

申请号：US15171890

申请日：2016-06-02

Applicant: Micron Technology, Inc.

Inventor： Zengtao T. Liu ,  Kirk D. Prall ,  Mike Violette

IPC: G11C11/00 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22

CPC classification number: H01L27/2436 ,  G11C5/063 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/222 ,  H01L27/228 ,  H01L27/24 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/10 ,  H01L45/065 ,  H01L45/085 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147

Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.

Abstract translation: 本公开包括包括电阻性存储器的方法和装置。 多个实施例包括耦合到数据线并包括第一电阻存储元件和第一存取器件的第一存储器单元，耦合到数据线并包括第二电阻存储元件和第二存取器件的第二存储单元， 形成在第一存取装置和第二存取装置之间的隔离装置，耦合到第一电阻存储元件的第一选择线和耦合到第二电阻存储元件的第二选择线，其中第二选择线与第一选择线分开 线。

公开(公告)号：US09123722B2

公开(公告)日：2015-09-01

申请号：US14177030

申请日：2014-02-10

Applicant: Micron Technology, Inc.

Inventor： Ming-Chuan Yang ,  Zengtao T. Liu ,  Vishal Sipani

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.

Abstract translation: 一些实施例包括形成互连的方法。 可以形成第一电路电平，并且可以在这样的第一电平上形成第一电介质区域。 可以在第一介电区域上形成第二级别的电路。 可以形成互连以延伸穿过这样的第二级。 可以在第二电平层上形成第二电介质区域，并且可以在第二电介质区域上形成第三电平的电路。 第三级电路可以通过互连电连接到第一级电路。 一些实施例包括具有从电路的第一电平延伸通过第二电平电平的开口到第三电平电平的互连的结构; 具有包括多个单独的导电柱的单独互连。

公开(公告)号：US09105636B2

公开(公告)日：2015-08-11

申请号：US13975503

申请日：2013-08-26

Applicant: Micron Technology, Inc.

Inventor： Zengtao T. Liu

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L27/10 ,  H01L23/532

CPC classification number: H01L21/76834 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming electrically conductive contacts. An opening is formed through an insulative material to a conductive structure. A conductive plug is formed within a bottom region of the opening. A spacer is formed to line a lateral periphery of an upper region of the opening, and to leave an inner portion of an upper surface of the plug exposed. A conductive material is formed against the inner portion of the upper surface of the plug. Some embodiments include semiconductor constructions having a conductive plug within an insulative stack and against a copper-containing material. A spacer is over an outer portion of an upper surface of the plug and not directly above an inner portion of the upper surface. A conductive material is over the inner portion of the upper surface of the plug and against an inner lateral surface of the spacer.

Abstract translation: 一些实施例包括形成导电触点的方法。 通过绝缘材料向导电结构形成开口。 导电插塞形成在开口的底部区域内。 形成间隔件以将开口的上部区域的侧边缘排列，并且使塞子的上表面的内部部分露出。 导电材料抵靠插塞的上表面的内部形成。 一些实施例包括在绝缘堆叠内具有导电插塞并且覆盖含铜材料的半导体结构。 间隔件在塞子的上表面的外部部分上方并且不在上表面的内部的正上方。 导电材料在插塞的上表面的内部部分上并且抵靠隔离件的内侧表面。

公开(公告)号：US09040379B2

公开(公告)日：2015-05-26

申请号：US14168898

申请日：2014-01-30

Applicant: Micron Technology, Inc.

Inventor： Zengtao T. Liu

IPC: H01L23/48 ,  H01L23/482 ,  H01L27/105 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L23/481 ,  H01L21/76829 ,  H01L21/76897 ,  H01L23/482 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect the lower portion of the etch stop structure, and the higher portion is removed. Subsequently, at least some of the first and second insulative materials are removed. Some embodiments include semiconductor constructions having a first region with first features, and a second region with second features. The first features are closer spaced than the second features. A first insulative material is over the second region and an insulative structure is over the first insulative material. The structure has a stem joined to a bench. The bench has an upper surface, and the stem extends to above the upper surface.

Abstract translation: 一些实施方案包括其中在衬底的存储区和外围区域形成第一绝缘材料的方法。 蚀刻停止结构形成为在存储区域上比在周边区域上具有更高的部分。 形成第二绝缘材料以保护蚀刻停止结构的下部，并且去除较高部分。 随后，去除第一和第二绝缘材料中的至少一些。 一些实施例包括具有具有第一特征的第一区域和具有第二特征的第二区域的半导体结构。 第一特征与第二特征相距更近。 第一绝缘材料在第二区域之上，绝缘结构超过第一绝缘材料。 该结构具有连接到工作台的杆。 工作台具有上表面，并且杆延伸到上表面上方。

公开(公告)号：US20140151902A1

公开(公告)日：2014-06-05

申请号：US14177030

申请日：2014-02-10

Applicant: Micron Technology, Inc.

Inventor： Ming-Chuan Yang ,  Zengtao T. Liu ,  Vishal Sipani

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.

Abstract translation: 一些实施例包括形成互连的方法。 可以形成第一电路电平，并且可以在这样的第一电平上形成第一电介质区域。 可以在第一介电区域上形成第二级别的电路。 可以形成互连以延伸穿过这样的第二级。 可以在第二电平层上形成第二电介质区域，并且可以在第二电介质区域上形成第三电平的电路。 第三级电路可以通过互连电连接到第一级电路。 一些实施例包括具有从电路的第一电平延伸通过第二电平电平的开口到第三电平电平的互连的结构; 具有包括多个单独的导电柱的单独互连。

公开(公告)号：US08680594B2

公开(公告)日：2014-03-25

申请号：US14017939

申请日：2013-09-04

Applicant: Micron Technology, Inc.

Inventor： Zengtao T. Liu

IPC: H01L27/108

CPC classification number: H01L23/481 ,  H01L21/76829 ,  H01L21/76897 ,  H01L23/482 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect the lower portion of the etch stop structure, and the higher portion is removed. Subsequently, at least some of the first and second insulative materials are removed. Some embodiments include semiconductor constructions having a first region with first features, and a second region with second features. The first features are closer spaced than the second features. A first insulative material is over the second region and an insulative structure is over the first insulative material. The structure has a stem joined to a bench. The bench has an upper surface, and the stem extends to above the upper surface.

Abstract translation: 一些实施方案包括其中在衬底的存储区和外围区域形成第一绝缘材料的方法。 蚀刻停止结构形成为在存储区域上比在周边区域上具有更高的部分。 形成第二绝缘材料以保护蚀刻停止结构的下部，并且去除较高部分。 随后，去除第一和第二绝缘材料中的至少一些。 一些实施例包括具有具有第一特征的第一区域和具有第二特征的第二区域的半导体结构。 第一特征与第二特征相距更近。 第一绝缘材料在第二区域之上，绝缘结构超过第一绝缘材料。 该结构具有连接到工作台的杆。 工作台具有上表面，并且杆延伸到上表面上方。

公开(公告)号：US20140008807A1

公开(公告)日：2014-01-09

申请号：US14017939

申请日：2013-09-04

Applicant: Micron Technology, Inc.

Inventor： Zengtao T. Liu

IPC: H01L23/482

CPC classification number: H01L23/481 ,  H01L21/76829 ,  H01L21/76897 ,  H01L23/482 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect the lower portion of the etch stop structure, and the higher portion is removed. Subsequently, at least some of the first and second insulative materials are removed. Some embodiments include semiconductor constructions having a first region with first features, and a second region with second features. The first features are closer spaced than the second features. A first insulative material is over the second region and an insulative structure is over the first insulative material. The structure has a stem joined to a bench. The bench has an upper surface, and the stem extends to above the upper surface.

Abstract translation: 一些实施方案包括其中在衬底的存储区和外围区域形成第一绝缘材料的方法。 蚀刻停止结构形成为在存储区域上比在周边区域上具有更高的部分。 形成第二绝缘材料以保护蚀刻停止结构的下部，并且去除较高部分。 随后，去除第一和第二绝缘材料中的至少一些。 一些实施例包括具有具有第一特征的第一区域和具有第二特征的第二区域的半导体结构。 第一特征与第二特征相距更近。 第一绝缘材料在第二区域之上，绝缘结构超过第一绝缘材料。 该结构具有连接到工作台的杆。 工作台具有上表面，并且杆延伸到上表面上方。