公开(公告)号：US20200013800A1

公开(公告)日：2020-01-09

申请号：US16526763

申请日：2019-07-30

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/11582 ,  H01L23/528 ,  H01L29/792 ,  H01L27/11573 ,  H01L29/10 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/311 ,  H01L21/321 ,  G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02 ,  H01L21/033 ,  H01L27/24 ,  H01L27/108 ,  G11C16/34

Abstract: A 3D memory device, the device including: a first horizontal bit-line; a second horizontal bit-line disposed above the first horizontal bit-line, where the first horizontal bit-line and the second horizontal bit-line function as a source or a drain for a plurality of parallel vertically-oriented memory transistors, where the first horizontal bit-line and the second horizontal bit-line are self-aligned being formed following the same lithography step; and conductive memory control lines, where a first portion of the conductive memory control lines are disposed at least partially directly underneath the plurality of parallel vertically-oriented memory transistors, and where a second portion of the conductive memory control lines are disposed at least partially directly above the plurality of parallel vertically-oriented memory transistors.

公开(公告)号：US20190244962A1

公开(公告)日：2019-08-08

申请号：US16377238

申请日：2019-04-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/10897 ,  H01L27/10802 ,  H01L27/10894 ,  H01L29/0649 ,  H01L29/7841

Abstract: A semiconductor device, the device including: a plurality of memory cells; and peripheral circuits, the peripheral circuits include controlling the plurality of memory cells, where each of the plurality of memory cells includes a first gate and a second gate, where the plurality of memory cells each include a channel region, at least one channel facet, a charge trap region and a tunneling region, where a portion of the peripheral circuits are designed to control the first gate and the second gate so to position two distinct memory sites, a first memory site and second a memory site, within the charge trap region of the at least one channel facet of at least one of the plurality of memory cells, and where the first memory site is substantially closer to the first gate than the second memory site.

公开(公告)号：US20190148286A1

公开(公告)日：2019-05-16

申请号：US16224674

申请日：2018-12-18

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11573

Abstract: A multilevel semiconductor device, including: a first level including a first array of first memory cells, each cell includes one first transistor; a second level including a second array of second memory cells, each cell includes one second transistor; a third level including a third array of third memory cells, each cell includes one third transistor, where second level overlays first level and third level overlays second level; memory control circuits connected so to individually control cells of the first, second and third memory cells, an array of units, each unit includes a plurality of the first, second and third memory cells and a portion of the memory control circuits, the array of units includes at least four rows and four columns of units, at least one of the first transistor is self-aligned to at least one of the third transistor, being formed following the same lithography step.

公开(公告)号：US20240349504A1

公开(公告)日：2024-10-17

申请号：US18527356

申请日：2023-12-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H10B43/27 ,  H01L23/528 ,  H01L27/02 ,  H01L29/167 ,  H01L29/47 ,  H01L29/78 ,  H01L29/792 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B53/20

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L27/0207 ,  H01L29/167 ,  H01L29/47 ,  H01L29/7827 ,  H01L29/792 ,  H10B43/10 ,  H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H10B53/20

Abstract: A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and at least one power-down control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

公开(公告)号：US12100658B2

公开(公告)日：2024-09-24

申请号：US18622992

申请日：2024-03-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H10B43/35 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method of making a 3D multilayer semiconductor device, the method comprising: providing a first substrate comprising a first level, said first level comprising a first single crystal silicon layer; providing a second substrate comprising a second level, said second level comprising a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of said second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of said SiGe layer; forming a plurality of second transistors each comprising a single crystal channel; forming a plurality of metal layers interconnecting said plurality of second transistors; and then performing a bonding of said second level onto said first level, wherein performing said bonding comprises making oxide-to-oxide bond zones, and performing removal of a majority of said second single crystal silicon layer.

公开(公告)号：US20240251572A1

公开(公告)日：2024-07-25

申请号：US18592383

申请日：2024-02-29

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer, a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed atop the plurality of third transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, and where the memory control circuit includes at least one digital to analog converter circuit.

公开(公告)号：US12035531B2

公开(公告)日：2024-07-09

申请号：US18516958

申请日：2023-11-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H10B43/27 ,  H01L23/528 ,  H01L27/02 ,  H01L29/167 ,  H01L29/47 ,  H01L29/78 ,  H01L29/792 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B53/20

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L27/0207 ,  H01L29/167 ,  H01L29/47 ,  H01L29/7827 ,  H01L29/792 ,  H10B43/10 ,  H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H10B53/20

Abstract: A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit which includes a plurality of first transistors; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors which include a metal gate are disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; and a memory array including word-lines, the memory array includes at least four memory mini arrays, each including at least four rows by at least four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, the memory control circuit includes at least one Look Up Table circuit (“LUT”).

公开(公告)号：US12029050B2

公开(公告)日：2024-07-02

申请号：US18389769

申请日：2023-12-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist ,  Eli Lusky

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A 3D semiconductor device including: a first level including a single crystal layer, and a memory control circuit which includes at least one temperature sensor circuit and first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors—which may include a metal gate—disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; a memory array including word-lines and at least four memory mini arrays (each mini array includes at least four rows by four columns of memory cells), each memory cell includes at least one second transistor or at least one third transistor; and a connection path from fourth metal to third metal, the path includes a via disposed through the memory array.

公开(公告)号：US20240096798A1

公开(公告)日：2024-03-21

申请号：US18389582

申请日：2023-11-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B10/00 ,  H10B12/00 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L25/0652 ,  H10B10/125 ,  H10B12/37 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00 ,  H01L2225/06541

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and is overlaying the first level; at least four electronic circuit units (ECUs); and a redundancy circuit, where each of the ECUs includes a first circuit which includes a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the at least four ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

公开(公告)号：US20240090225A1

公开(公告)日：2024-03-14

申请号：US18516958

申请日：2023-11-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H10B43/27 ,  H01L23/528 ,  H01L27/02 ,  H01L29/167 ,  H01L29/47 ,  H01L29/78 ,  H01L29/792 ,  H10B43/10 ,  H10B43/20

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L27/0207 ,  H01L29/167 ,  H01L29/47 ,  H01L29/7827 ,  H01L29/792 ,  H10B43/10 ,  H10B43/20 ,  H10B41/10

Abstract: A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit which includes a plurality of first transistors; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors which include a metal gate are disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; and a memory array including word-lines, the memory array includes at least four memory mini arrays, each including at least four rows by at least four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, the memory control circuit includes at least one Look Up Table circuit (“LUT”).