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公开(公告)号：US09383998B2
公开(公告)日：2016-07-05
申请号：US13440096
申请日：2012-04-05
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
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公开(公告)号：US08700937B2
公开(公告)日：2014-04-15
申请号：US12755339
申请日：2010-04-06
申请人： Deep Buch , Vivek Garg , Subramaniam Maiyuran
发明人： Deep Buch , Vivek Garg , Subramaniam Maiyuran
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , G06F1/3287
摘要： A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.
摘要翻译： 描述了一种方法，其涉及通过一个无孔部来控制交通等级，以提供对该无孔的热管理。 所述方法包括确定第一非核状态中的非空气温度是否高于第一阈值，并且如果所述非空温度高于所述第一阈值，则将所述第一非空状态改变为第二非空状态。
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公开(公告)号：US07958284B2
公开(公告)日：2011-06-07
申请号：US11363650
申请日：2006-02-28
摘要： Methods and apparatus to transfer data between one or more clock domains are described. In one embodiment, a plurality of signals corresponding to write pointers of a buffer and a read pointer of the buffer are generated. The signals corresponding to the write pointers of the buffer are to be generated based on different data patterns for transmission over different channels. Other embodiments are also claimed and described.
摘要翻译： 描述了在一个或多个时钟域之间传送数据的方法和装置。 在一个实施例中，产生对应于缓冲器的写指针和缓冲器的读指针的多个信号。 将根据不同的数据模式生成与缓冲器的写指针对应的信号，以便在不同的通道上进行传输。 还要求保护和描述其它实施例。
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54.发明授权Power-performance modulation in caches using a smart least recently used scheme 失效使用智能最近最近使用的方案在高速缓存中进行功率性能调制公开(公告)号：US07689772B2
公开(公告)日：2010-03-30
申请号：US11418883
申请日：2006-05-04
CPC分类号： G06F12/0864 , G06F12/123 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： The number of ways in an N-way set associative sequential cache is modulated to trade power and performance. Way selection is restricted during the allocation based on address so that only a subset of the N-ways is used for a range of addresses allowing the N-ways that are not in use to be powered off.
摘要翻译： N路集合关联顺序高速缓存中的方式的数量被调制以交易功率和性能。 在基于地址的分配期间，路由选择被限制，使得只有N个路径的子集被用于允许不使用的N路被关闭的一系列地址。
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公开(公告)号：US20070201592A1
公开(公告)日：2007-08-30
申请号：US11363650
申请日：2006-02-28
IPC分类号： H04L7/00
摘要： Methods and apparatus to transfer data between one or more clock domains are described. In one embodiment, a signal corresponding to a read pointer of a buffer is generated in response to a plurality of signals that correspond to write pointers of the buffer.
摘要翻译： 描述了在一个或多个时钟域之间传送数据的方法和装置。 在一个实施例中，响应于对应于缓冲器的写指针的多个信号而产生对应于缓冲器的读指针的信号。
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56.发明授权Apparatus, method, and system for synchronizing information prefetch between processors and memory controllers 失效用于在处理器和存储器控制器之间同步信息预取的装置，方法和系统公开(公告)号：US06898674B2
公开(公告)日：2005-05-24
申请号：US10170171
申请日：2002-06-11
CPC分类号： G06F12/0215 , G06F12/0862 , G06F13/161 , G06F2212/6026 , G06F2212/6028
摘要： According to one embodiment of the invention, a prefetcher in a memory controller is described which includes logic to receive memory request hints from a CPU. The memory request hints are used by the prefetcher in the memory controller to prefetch information from one or more memory devices coupled to the memory controller via a memory bus. The prefetcher in the memory controller further includes logic to determine the types of memory request hints provided by the CPU, the types of memory request hints are used to indicate whether the hints provided by the CPU are for instruction memory read request or data memory read request. The prefetcher in the memory controller also includes logic to generate prefetch requests to prefetch information from the one or more memory devices, based on the types of memory request hints provided by the CPU and bandwidth availability of the memory bus.
摘要翻译： 根据本发明的一个实施例，描述了存储器控制器中的预取器，其包括从CPU接收存储器请求提示的逻辑。 存储器请求提示被存储器控制器中的预取器用于从经由存储器总线耦合到存储器控制器的一个或多个存储器件预取信息。 存储器控制器中的预取器还包括确定由CPU提供的存储器请求提示的类型的逻辑，存储器请求提示的类型用于指示由CPU提供的提示是用于指令存储器读请求还是数据存储器读请求 。 存储器控制器中的预取器还包括基于由CPU提供的存储器请求提示的类型和存储器总线的带宽可用性来生成预取请求以从一个或多个存储器设备预取信息的逻辑。
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公开(公告)号：US20050097277A1
公开(公告)日：2005-05-05
申请号：US11000054
申请日：2004-12-01
CPC分类号： G06F12/0864 , G06F12/0846 , G06F2212/1028 , Y02D10/13
摘要： In a processor cache, cache circuits are mapped into one or more logical modules. Each module may be powered down independently of other modules in response to microinstructions processed by the cache. Power control may be applied on a microinstruction-by-microinstruction basis. Because the microinstructions determine which modules are used, power savings may be achieved by powering down those modules that are not used. A cache layout organization may be modified to distribute a limited number of ways across addressable cache banks. By associating fewer than a total number of ways to a bank (for example, one or two ways), the size of memory clusters within the bank may be reduced. The reduction in this size of the memory cluster contributes reduces the power needed for an address decoder to address sets within the bank.
摘要翻译： 在处理器高速缓存中，高速缓存电路被映射到一个或多个逻辑模块中。 响应于由高速缓存处理的微指令，每个模块可以独立于其它模块被关闭。 功率控制可以在微指令的基础上应用。 因为微指令决定了哪些模块被使用，所以可以通过关闭那些未使用的模块来实现功率节省。 可以修改高速缓存布局组织以在可寻址缓存组中分布有限数量的方式。 通过将小于总数量的方式与银行相关联（例如，一种或两种方式），可以减少银行内的存储器簇的大小。 存储器簇的这种尺寸的减小有助于减少地址解码器对存储体内的集合进行寻址所需的功率。
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公开(公告)号：US06643745B1
公开(公告)日：2003-11-04
申请号：US09053383
申请日：1998-03-31
申请人： Salvador Palanca , Niranjan L. Cooray , Angad Narang , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran , Jagannath Keshava , Hsien-Hsin Lee , Steve Spangler , Suresh Kuttuva , Praveen Mosur
发明人： Salvador Palanca , Niranjan L. Cooray , Angad Narang , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran , Jagannath Keshava , Hsien-Hsin Lee , Steve Spangler , Suresh Kuttuva , Praveen Mosur
IPC分类号： G06F1200
CPC分类号： G06F9/383 , G06F9/3842 , G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.
摘要翻译： 公开了一种计算机系统。 计算机系统包括较高级别的缓存，较低级别的缓存，解码指令的解码器以及耦合到解码器的电路。 在一个实施例中，电路响应于单个解码的指令，在较高级别的高速缓存未命中时从外部存储器检索数据并绕过下一级高速缓存。 在另一个实施例中，电路响应于第一解码指令发出从外部存储器的地址检索数据的请求，以将所述数据仅放置在较低级别的高速缓存中，检测到所述地址的第二可缓存解码指令， 表示高级缓存中的数据。
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公开(公告)号：US06216215B1
公开(公告)日：2001-04-10
申请号：US09053932
申请日：1998-04-02
IPC分类号： G06F930
CPC分类号： G06F9/3857 , G06F9/30047 , G06F9/3824 , G06F9/3834 , G06F13/1668
摘要： The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is executed after retiring.
摘要翻译： 本发明公开了一种实现高级加载指令类型的方法和装置。 解码请求存储器参考的指令。 然后将解码的指令分派到存储器订购单元。 该指令从加载缓冲区中退出，并在退出后执行。
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公开(公告)号：US06175253B1
公开(公告)日：2001-01-16
申请号：US09052883
申请日：1998-03-31
IPC分类号： H03K1902
CPC分类号： H03K19/018592 , H03K19/09429
摘要： A driver to drive a bus with a pullup and a pulldown transistor according to a data signal during a drive phase and to charge or discharge the bus to intermediate voltage levels during a precondition phase using the pullup and pulldown transistors, the driver comprising a buffer and latch to latch the bus voltage at the end of a drive phase; a precondition circuit responsive to the latch to switch ON a pullup transistor at the beginning of a precondition phase when the bus voltage was LOW in the previous drive phase so as to charge the bus voltage to a first voltage less than a supply voltage, and to switch ON a pulldown transistor at the beginning of the precondition phase when the bus voltage was HIGH in the previous drive phase so as to discharge the bus voltage to a second voltage above ground.
摘要翻译： 驱动器，其在驱动阶段期间根据数据信号驱动具有上拉和下拉晶体管的总线，并且在使用所述上拉和下拉晶体管的前提阶段期间将所述总线充电或放电到中间电压电平，所述驱动器包括缓冲器和 在驱动阶段结束时锁存总线电压; 当前一个驱动阶段的总线电压为低电平时，响应锁存器的开关状态，在预处理阶段开始时接通上拉晶体管，以便将总线电压充电到小于电源电压的第一电压， 在前一个驱动阶段的总线电压为高电平时，在预处理阶段开始时，接通一个下拉晶体管，以便将总线电压放电到地面以上的第二个电压。
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