公开(公告)号：US06515507B1

公开(公告)日：2003-02-04

申请号：US09607569

申请日：2000-06-29

申请人： Rakesh H. Patel ,  Thomas H. White

发明人： Rakesh H. Patel ,  Thomas H. White

IPC分类号： G06F738

CPC分类号： G11C16/30 ,  G11C5/147 ,  G11C16/20 ,  H03K3/011 ,  H03K3/0315

摘要： An integrated circuit has one or more external control pins to control and indicate which of two or more different VCC or other voltage levels will be used. The control pin receives a logic signal, high or low, and draws zero static power. A user can use the integrated circuit with two or more VCC voltage levels by indicating which voltage level at the control pins. In a specific embodiment, the integrated circuit has nonvolatile memory cells such as EEPROM or Flash cells that a configurable and reconfigurable using on-chip programming circuitry. The programming circuitry may generate and use superhigh or high voltages, higher than the VCC voltage.

摘要翻译： 集成电路具有一个或多个外部控制引脚，用于控制并指示将使用两个或多个不同VCC或其他电压电平中的哪一个。 控制引脚接收高或低的逻辑信号，并绘制零静态功率。 用户可以通过指示控制引脚上的哪个电压电平，使用具有两个或多个VCC电压电平的集成电路。 在具体实施例中，集成电路具有非易失性存储单元，例如EEPROM或闪存单元，其是使用片上编程电路的可配置和可重新配置的。 编程电路可以产生和使用高于VCC电压的超高电压或高电压。

公开(公告)号：US06317367B1

公开(公告)日：2001-11-13

申请号：US09748088

申请日：2000-12-21

申请人： Stephen P. Sample ,  Michael R. Butts ,  Kevin A. Norman ,  Rakesh H. Patel ,  Chao Chiang Chen

发明人： Stephen P. Sample ,  Michael R. Butts ,  Kevin A. Norman ,  Rakesh H. Patel ,  Chao Chiang Chen

IPC分类号： G11C700

CPC分类号： H03K19/17772 ,  G11C7/1006 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/16 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

摘要： An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has multiple blocks of multiported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multiported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.

摘要翻译： 如本文所述的用于实现可重配置逻辑的集成电路，例如现场可编程门阵列（“FPGA”）具有多个多端口存储器块。 存储器具有多个读取端口和多个写入端口。 多端口存储器的每个端口可以配置为与其他端口的宽度和深度独立且独立的宽度和深度。 该存储器还包括用于对存储器的内容进行同步快照或将存储器加载到初始状态的端口。 存储器共享由低级逻辑元件使用的路由线，从而减轻了为了满足存储器需求而向互连网络添加路由线路的需要。

公开(公告)号：US5870410A

公开(公告)日：1999-02-09

申请号：US840357

申请日：1997-04-28

申请人： Kevin A. Norman ,  Rakesh H. Patel ,  Stephen P. Sample ,  Michael R. Butts

发明人： Kevin A. Norman ,  Rakesh H. Patel ,  Stephen P. Sample ,  Michael R. Butts

IPC分类号： G01R31/28

CPC分类号： G01R31/318516

摘要： An diagnostic interface system for a programmable logic system is disclosed. The diagnostic interface system provides an efficient and flexible mechanism for accessing internal nodes of programmable logic devices (PLDs) to facilitate debugging and troubleshooting of the programmable logic system. The interface system includes a diagnostic data bus connecting external I/O pins to various diagnostic data and address registers that connect to the internal circuitry of a PLD. A diagnostics controller controls the various diagnostic resources in response to user supplied control data.

摘要翻译： 公开了一种用于可编程逻辑系统的诊断接口系统。 诊断接口系统为访问可编程逻辑器件（PLD）的内部节点提供了一种有效且灵活的机制，以便于可编程逻辑系统的调试和故障排除。 接口系统包括将外部I / O引脚连接到各种诊断数据的诊断数据总线和连接到PLD内部电路的地址寄存器。 诊断控制器根据用户提供的控制数据控制各种诊断资源。

公开(公告)号：US5869980A

公开(公告)日：1999-02-09

申请号：US896146

申请日：1997-07-17

申请人： Michael Hsiao-Ming Chu ,  Rakesh H. Patel

发明人： Michael Hsiao-Ming Chu ,  Rakesh H. Patel

IPC分类号： G01R31/3185 ,  G06F17/50 ,  G11C29/32 ,  G11C29/44 ,  G11C29/48 ,  G11C29/52 ,  H03K19/177

CPC分类号： G11C29/48 ,  G01R31/318561 ,  G06F17/5054 ,  G11C29/44 ,  G11C29/52 ,  G11C29/32

摘要： An integrated circuit with programmable transistors is programmed via a state machine on the integrated circuit. For example, the integrated circuit may be a programmable logic device, and the state machine may be a JTAG state machine. Each integrated circuit may have on it a register containing data indicating how long a particular programming operation should continue in order to be successful for that circuit. External programming control apparatus first reads that data and then at least partly bases the timing of programming instructions applied to the integrated circuit on that data. The integrated circuit may have an on-board programming voltage generating circuit which is turned on only by appropriate instructions from the external programming control apparatus. The external programming control apparatus controls the sequence and timing of all programming operations via the state machine port of the integrated circuit.

摘要翻译： 具有可编程晶体管的集成电路通过集成电路上的状态机进行编程。 例如，集成电路可以是可编程逻辑器件，并且状态机可以是JTAG状态机。 每个集成电路可以在其上具有包含指示特定编程操作应该持续多久才能使该电路成功的数据的寄存器。 外部编程控制装置首先读取数据，然后至少部分地基于应用于该数据的集成电路的编程指令的定时。 集成电路可以具有仅通过来自外部编程控制装置的适当指令而导通的板上编程电压产生电路。 外部编程控制装置经由集成电路的状态机端口控制所有编程操作的顺序和定时。

公开(公告)号：US5821771A

公开(公告)日：1998-10-13

申请号：US651101

申请日：1996-05-21

申请人： Rakesh H. Patel ,  John Costello ,  Myron Wong

发明人： Rakesh H. Patel ,  John Costello ,  Myron Wong

IPC分类号： H03K19/177 ,  H03K17/00

CPC分类号： H03K19/17764 ,  H03K19/1778 ,  H03K19/17784

摘要： A system and method for programming elements in an integrated circuit. The system allows for selection of an internal voltage supply and an external supply. Provision is also possible for improved testing techniques.

摘要翻译： 一种用于在集成电路中编程元件的系统和方法。 该系统允许选择内部电源和外部电源。 提供改进的测试技术也是可行的。

公开(公告)号：US5350954A

公开(公告)日：1994-09-27

申请号：US39927

申请日：1993-03-29

申请人： Rakesh H. Patel

发明人： Rakesh H. Patel

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1736 ,  H03K19/1737

摘要： An improved macrocell is provided for summing product term inputs to complete a sum of products. Some or all of a macrocell's product terms can be allocated to another macrocell. The macrocell OR function remains available to sum product term inputs, even when other product term inputs in the same macrocell are allocated elsewhere. Macrocells can also by daisy-chained bidirectionally, so that the delay associated with allocating product terms between multiple macrocells can be reduced.

摘要翻译： 提供了一个改进的宏单元，用于对产品项输入进行求和以完成一个乘积。 宏单元的产品术语中的一些或全部可以被分配给另一宏单元。 宏单元OR功能仍然可用于对产品项输入进行求和，即使同一宏单元中的其他产品项输入在其他地方分配。 宏单元还可以通过双向菊花链连接，从而可以减少与在多个宏小区之间分配产品项的相关延迟。

公开(公告)号：US08719753B1

公开(公告)日：2014-05-06

申请号：US12703681

申请日：2010-02-10

申请人： Francis Man-Chit Chow ,  Rakesh H. Patel ,  Erhard Joachim Pistorius

发明人： Francis Man-Chit Chow ,  Rakesh H. Patel ,  Erhard Joachim Pistorius

IPC分类号： G06F17/50

CPC分类号： H03K19/17796 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.

公开(公告)号：US07646217B2

公开(公告)日：2010-01-12

申请号：US11539006

申请日：2006-10-05

申请人： Ramanand Venkata ,  Rakesh H. Patel ,  Chong H. Lee

发明人： Ramanand Venkata ,  Rakesh H. Patel ,  Chong H. Lee

IPC分类号： H01L25/00

CPC分类号： H03K19/17736 ,  H03K19/17744 ,  H03K19/17784

摘要： In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.

摘要翻译： 在可编程逻辑器件中，部分或全部并行互连资源由器件内的串行互连资源代替。 设备上的部分或全部功能块被补充有串行接口。 尽管这使得功能块更加复杂，但它允许显着减少互连资源消耗的面积。 这意味着设备功耗的显着降低。 串行接口可以与全局设备时钟（例如PLL）同步工作。 在某些情况下，可以省略输入/输出块中提供的用于外部信号的串行接口，因为功能块中的串行接口也可以接管外部串行接口功能，尽管在这些情况下，功能中的串行接口 块将不得不更复杂，因为它们必须能够与外部设备异步操作。

公开(公告)号：US20090315627A1

公开(公告)日：2009-12-24

申请号：US12142746

申请日：2008-06-19

申请人： William W. Bereza ,  Rakesh H. Patel

发明人： William W. Bereza ,  Rakesh H. Patel

IPC分类号： H03L7/00

CPC分类号： H03L7/099 ,  H03L7/18

摘要： Configurable phase-locked loop circuitry is provided. The phase-locked loop circuitry may include a buffer having a buffer output and a multiplexer having inputs and an output. The phase-locked loop circuitry may include multiple voltage-controlled oscillators. The phase-locked loop circuitry may be configured to switch a desired one of the voltage-controlled oscillators into use. Each voltage-controlled oscillator may be controlled by control signals applied to a control input for that voltage-controlled oscillator. The control input of each voltage-controlled oscillator may be connected to the buffer output. The output of each voltage-controlled oscillator may be connected to a respective one of the multiplexer inputs. Power-down transistors may be used to disable unused voltage-controlled oscillators to conserve power. The power-down transistors and the multiplexer may be controlled by signals from programmable elements. One or more of the voltage-controlled oscillators may be implemented using a separate integrated circuit connected using through-silicon vias.

摘要翻译： 提供可配置的锁相环电路。 锁相环电路可以包括具有缓冲器输出的缓冲器和具有输入和输出的多路复用器。 锁相环电路可以包括多个压控振荡器。 锁相环电路可以被配置为将期望的一个压控振荡器切换成使用。 每个压控振荡器可以由施加到该压控振荡器的控制输入的控制信号来控制。 每个压控振荡器的控制输入可以连接到缓冲器输出端。 每个压控振荡器的输出可以连接到多路复用器输入中的相应一个。 掉电晶体管可用于禁用未使用的电压控制振荡器以节省功率。 掉电晶体管和多路复用器可以由来自可编程元件的信号控制。 可以使用通过硅通孔连接的单独的集成电路来实现一个或多个压控振荡器。

公开(公告)号：US06831480B1

公开(公告)日：2004-12-14

申请号：US10338920

申请日：2003-01-07

申请人： Sergey Y. Shumarayev ,  Rakesh H. Patel

发明人： Sergey Y. Shumarayev ,  Rakesh H. Patel

IPC分类号： G06F738

CPC分类号： H03K19/177

摘要： Programmable logic device integrated circuitry having I/O circuitry portions having different maximum speed capabilities and different amounts of programmability for supporting various I/O signaling standards is provided. High-speed I/O circuitry and low-speed I/O circuitry may be provided. The high-speed I/O circuitry may have differential I/O drivers and may not be programmable. Relatively few I/O lines may be connected to the high-speed I/O circuitry. The low-speed I/O circuitry may be programmable so that a user may configure the low-speed I/O circuitry to support different I/O signaling standards. Intermediate-speed I/O circuitry may be provided that is more flexible than the high-speed circuitry and operates at higher maximum I/O data rates than the low-speed I/O circuitry. Transmitter circuitry (output driver circuitry) in the I/O circuitry may be provided with the ability to handle a greater number of different I/O signaling standards than receiver circuitry (input driver circuitry) in the I/O circuitry.

摘要翻译： 提供了具有不同最大速度能力的I / O电路部分和用于支持各种I / O信令标准的不同数量的可编程性的可编程逻辑器件集成电路。 可以提供高速I / O电路和低速I / O电路。 高速I / O电路可能具有差分I / O驱动器，可能无法编程。 相对较少的I / O线可能连接到高速I / O电路。 低速I / O电路可以是可编程的，使得用户可以配置低速I / O电路以支持不同的I / O信令标准。 可以提供比高速电路更灵活的中速I / O电路，并且以比低速I / O电路更高的最大I / O数据速率工作。 I / O电路中的发射机电路（输出驱动器电路）可以具有处理比I / O电路中的接收机电路（输入驱动器电路）更多数量的不同I / O信令标准的能力。