公开(公告)号：US09471518B2

公开(公告)日：2016-10-18

申请号：US13667520

申请日：2012-11-02

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Wendemagegnehu Beyene

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G06F13/1668 ,  G11C7/1057 ,  G11C7/1084

Abstract: A multi-modal memory interface that supports each of current-mode and voltage-mode signaling by a memory controller with a memory which includes one or more memory devices. In a first type of system, the memory interface is configured to provide differential current-mode signaling from the memory controller to a first type of memory, and differential voltage-mode signaling from the memory to the memory controller. In contrast, in a second type of system, the memory interface is configured to provide single-ended voltage-mode signaling from the memory controller to the memory, and single-ended voltage-mode signaling from a second type of memory to the memory controller. To support these different types of systems, the memory controller couples different types of drivers to each I/O pad. The resulting capacitance is reduced by sharing components between these drivers. Moreover, in some embodiments, the memory interface is implemented using “near-ground” current-mode and voltage-mode signaling techniques.

Abstract translation: 一种多模式存储器接口，其通过包括一个或多个存储器件的存储器由存储器控制器支持每个电流模式和电压模式信号。 在第一类型的系统中，存储器接口被配置为提供从存储器控制器到第一类型存储器的差分电流模式信号，以及从存储器到存储器控制器的差分电压模式信令。 相比之下，在第二类型的系统中，存储器接口被配置为提供从存储器控制器到存储器的单端电压模式信令，以及从第二类型存储器到存储器控制器的单端电压模式信令 。 为了支持这些不同类型的系统，存储器控制器将不同类型的驱动器耦合到每个I / O焊盘。 通过在这些驱动器之间共享组件来减小所产生的电容。 此外，在一些实施例中，使用“近地”电流模式和电压模式信令技术来实现存储器接口。

公开(公告)号：US20150309517A1

公开(公告)日：2015-10-29

申请号：US14699780

申请日：2015-04-29

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Michael D. Bucher ,  Lei Luo ,  Chaofeng Charlie Huang ,  Amir Amirkhany ,  Huy M. Nguyen ,  Hsuan-Jung (Bruce) Su ,  John Wilson

IPC: G05F1/46

CPC classification number: G05F1/462 ,  G11C5/147

Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.

Abstract translation: 集成电路包括用于提供调节电压的电压调节器和耦合到未终端传输线的数据输出。 该电路根据数据从电压调节器抽取可变量的功率。 电压调节器包括用于提供数据转变相关电流的第一电流产生电路。

公开(公告)号：US20150212953A1

公开(公告)日：2015-07-30

申请号：US14683080

申请日：2015-04-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/16 ,  G11C7/10 ,  G11C5/02

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/02 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract translation: 半导体存储器系统包括第一半导体存储器管芯和第二半导体存储器管芯。 第一半导体存储器管芯包括主数据接口，用于在写操作期间接收输入数据流，并将输入数据流反序列化为第一多个数据流，并且还包括耦合到主数据接口的辅数据接口， 发送第一多个数据流。 第二半导体存储器管芯包括耦合到第一半导体存储器管芯的次级数据接口的次级数据接口，以接收第一多个数据流。

公开(公告)号：US20150179248A1

公开(公告)日：2015-06-25

申请号：US14405910

申请日：2013-06-10

Applicant: RAMBUS INC.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G11C11/4076

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272 ,  H03L7/0816

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract translation: 实施例通常涉及存储器件。 在一个实施例中，存储器件包括时钟接收器电路，其接收外部时钟信号并提供内部时钟信号。 存储装置还包括具有输入的延迟锁定环路电路（DLL）和接收内部时钟信号的电路。 该电路选择内部时钟信号的哪些脉冲被施加到DLL的输入端，使得从外部时钟信号的至少三个连续脉冲中选出的不超过两个时钟脉冲在预定的时间内被施加到DLL的输入 间隔。 在另一个实施例中，一种方法包括在时钟接收器电路处接收外部时钟信号，从时钟接收器电路接收内部时钟信号，以及选择内部时钟信号的哪些脉冲被施加到DLL的输入，其中不再有 从外部时钟信号的至少三个连续脉冲中选择的两个时钟脉冲在预定间隔期间被施加到DLL的输入端。

公开(公告)号：US20140347092A1

公开(公告)日：2014-11-27

申请号：US14368772

申请日：2012-12-22

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Farshid Aryanfar ,  Ravindranath Kollipara ,  Xingchao (Chuck) Yuan

IPC: H03K19/00

CPC classification number: H03K19/0005 ,  G06F13/4086 ,  G11C29/50008 ,  H03K19/017545 ,  H04L25/0278

Abstract: Alternating on-die termination impedances are applied within an integrated circuit device to up-convert signal reflections to higher frequencies that are attenuated by the signaling channel as the reflections propagate toward an intended signal receiver. Through this approach, the disruptive effect of reflected signals may be significantly reduced with relatively little overhead within the interconnected integrated circuit devices and little or no change to the printed circuit board or other interconnect medium. Changes to the printed circuit board or other interconnect medium can be made to further increase attenuation over the frequency band of the up-converted reflection and outside of the transmission band of signals of interest.

Abstract translation: 在集成电路器件内施加交替的片上终端阻抗，以将信号反射上变频到由信号通道衰减的较高频率，因为反射向预期信号接收器传播。 通过这种方法，相互连接的集成电路器件内的相对较少的开销可以显着降低反射信号的破坏性影响，并且对印刷电路板或其它互连介质几乎没有或没有改变。 可以对印刷电路板或其它互连介质进行改变，以进一步增加在上变频反射的频带和感兴趣的信号的传输频带之外的衰减。

公开(公告)号：US20140023161A1

公开(公告)日：2014-01-23

申请号：US13937549

申请日：2013-07-09

Applicant: Rambus Inc.

Inventor： Reza Navid ,  Amir Amirkhany ,  Dinesh D. Patil ,  Brian S. Leibowitz

IPC: H04L1/00

CPC classification number: H04L1/0083 ,  H04L1/0001 ,  H04L1/0002 ,  H04L1/0007

Abstract: Data coding schemes perform level-based and/or transition-based encoding to avoid signaling conditions that create worst case crosstalk during transmission of multi-bit data from one circuit to another circuit via a parallel communication link. The coding schemes disallow certain patterns from being present in the signal levels, signal transitions, or a combination of the signal levels and signal transitions that occur in a subset of the multi-bit data that corresponds to certain physically neighboring wires of the parallel communication link.

Abstract translation: 数据编码方案执行基于电平和/或基于转换的编码，以避免在通过并行通信链路将多位数据从一个电路传输到另一电路时产生最差情况串扰的信令条件。 编码方案不允许某些模式存在于信号电平，信号转换或信号电平和信号转换的组合中，信号电平和信号转换发生在对应于并行通信链路的某些物理相邻电线的多位数据的子集中 。

公开(公告)号：US20130114363A1

公开(公告)日：2013-05-09

申请号：US13667520

申请日：2012-11-02

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Wendemagegnehu Beyene

IPC: G11C7/00

CPC classification number: G06F13/1668 ,  G11C7/1057 ,  G11C7/1084

Abstract: A multi-modal memory interface that supports each of current-mode and voltage-mode signaling by a memory controller with a memory which includes one or more memory devices. In a first type of system, the memory interface is configured to provide differential current-mode signaling from the memory controller to a first type of memory, and differential voltage-mode signaling from the memory to the memory controller. In contrast, in a second type of system, the memory interface is configured to provide single-ended voltage-mode signaling from the memory controller to the memory, and single-ended voltage-mode signaling from a second type of memory to the memory controller. To support these different types of systems, the memory controller couples different types of drivers to each I/O pad. The resulting capacitance is reduced by sharing components between these drivers. Moreover, in some embodiments, the memory interface is implemented using “near-ground” current-mode and voltage-mode signaling techniques.

Abstract translation: 一种多模式存储器接口，其通过包括一个或多个存储器件的存储器由存储器控制器支持每个电流模式和电压模式信号。 在第一类型的系统中，存储器接口被配置为提供从存储器控制器到第一类型存储器的差分电流模式信号，以及从存储器到存储器控制器的差分电压模式信令。 相比之下，在第二类型的系统中，存储器接口被配置为提供从存储器控制器到存储器的单端电压模式信令，以及从第二类型存储器到存储器控制器的单端电压模式信令 。 为了支持这些不同类型的系统，存储器控制器将不同类型的驱动器耦合到每个I / O焊盘。 通过在这些驱动器之间共享组件来减小所产生的电容。 此外，在一些实施例中，使用“近地”电流模式和电压模式信令技术来实现存储器接口。