Semiconductor memory device
    52.
    发明授权

    公开(公告)号:US11917805B2

    公开(公告)日:2024-02-27

    申请号:US17541584

    申请日:2021-12-03

    CPC classification number: H10B12/00

    Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.

    Semiconductor memory devices
    54.
    发明授权

    公开(公告)号:US11887648B2

    公开(公告)日:2024-01-30

    申请号:US17362138

    申请日:2021-06-29

    Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

    3D FERROELECTRIC MEMORY DEVICES
    57.
    发明公开

    公开(公告)号:US20230309314A1

    公开(公告)日:2023-09-28

    申请号:US18108374

    申请日:2023-02-10

    CPC classification number: H10B51/20 H10B51/10 H01L29/516 H01L29/78391

    Abstract: A three-dimensional ferroelectric random access memory (3D FeRAM) device includes: a gate electrode extending in a vertical direction on a substrate; a ferroelectric pattern and a gate insulation pattern stacked on the gate electrode in a horizontal direction to surround the gate electrode; first and second channels spaced apart from each other in the horizontal direction on an outer sidewall of the gate insulation pattern; first source/drain pattern structures spaced apart from each other in the vertical direction on an outer sidewall of the first channel; and second source/drain pattern structures spaced apart from each other in the vertical direction on an outer sidewall of the second channel.

    Robot cleaner
    58.
    发明授权

    公开(公告)号:US11659971B2

    公开(公告)日:2023-05-30

    申请号:US16891673

    申请日:2020-06-03

    Abstract: Disclosed are a robot cleaner. The robot cleaner includes: a cleaner body configured to move in an area and clean the area; and a sensor assembly provided in the cleaner body. The sensor assembly includes: a main sensor configured to be moveable between a sensing position where the main sensor protrudes out of the cleaner body and a settled position where the main sensor is inside the cleaner body; a sensor position changer configured to allow the main sensor to move between the sensing position and the settled position; and a stopper configured to restrict the sensor position changer from allowing the main sensor at the sensing position to move towards the settled position.

    SEMICONDUCTOR DEVICES INCLUDING SEMICONDUCTOR PATTERN

    公开(公告)号:US20230163132A1

    公开(公告)日:2023-05-25

    申请号:US18098174

    申请日:2023-01-18

    CPC classification number: H01L27/1027 H01L29/742

    Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

    SEMICONDUCTOR DEVICE
    60.
    发明申请

    公开(公告)号:US20230075559A1

    公开(公告)日:2023-03-09

    申请号:US17741219

    申请日:2022-05-10

    Abstract: A semiconductor device includes: a channel; a gate structure on the channel; a first source/drain arranged at a first end of the channel and including a metal; a first tunable band-gap layer arranged between the channel and the first source/drain and having a band gap that changes according to stress; a first electrostrictive layer between the gate structure and the first tunable band-gap layer, the first electrostrictive layer having a property of being deformed based on and upon application of an electric field; and a second source/drain at a second end of the channel.

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