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公开(公告)号:US11943925B2
公开(公告)日:2024-03-26
申请号:US17335763
申请日:2021-06-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyuncheol Kim , Jaeho Hong , Yongseok Kim , Ilgweon Kim , Hyeoungwon Seo , Sungwon Yoo , Kyunghwan Lee
IPC: G11C8/14 , G11C7/18 , H01L25/065 , H10B43/10 , H10B43/27
CPC classification number: H10B43/27 , G11C7/18 , G11C8/14 , H01L25/065 , H10B43/10
Abstract: A semiconductor memory device includes first conductive lines stacked in a first direction perpendicular to a top surface of a substrate, second conductive lines extending in the first direction and intersecting the first conductive lines, and memory cells provided at intersection points between the first conductive lines and the second conductive lines, respectively. Each of the memory cells includes a semiconductor pattern parallel to the top surface of the substrate, the semiconductor pattern including a source region having a first conductivity type, a drain region having a second conductivity type, and a channel region between the source region and the drain region, first and second gate electrodes surrounding the channel region of the semiconductor pattern, and a charge storage pattern between the semiconductor pattern and the first and second gate electrodes.
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公开(公告)号:US11917805B2
公开(公告)日:2024-02-27
申请号:US17541584
申请日:2021-12-03
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyunghwan Lee , Yongseok Kim , Ilgweon Kim , Huijung Kim , Sungwon Yoo , Minhee Cho
IPC: H10B12/00
CPC classification number: H10B12/00
Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.
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公开(公告)号:US11910213B2
公开(公告)日:2024-02-20
申请号:US18181971
申请日:2023-03-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyunseok Ryu , Yongseok Kim , Peng Xue , Hyunkyu Yu , Sangwon Choi , Kuyeon Whang
CPC classification number: H04W24/08 , H04L5/0048 , H04L5/0053 , H04L5/0094 , H04W72/21 , H04W74/04 , H04W74/0833 , H04W76/27 , H04L5/001 , H04L5/0023 , H04L5/0035 , H04L5/0064 , H04L5/14 , H04W74/008
Abstract: A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided, which may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An uplink transmission method is provided, which can increase an uplink coverage through improvement of reception reliability of uplink control information and data information.
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公开(公告)号:US11887648B2
公开(公告)日:2024-01-30
申请号:US17362138
申请日:2021-06-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jaeho Hong , Hyuncheol Kim , Yongseok Kim , Ilgweon Kim , Hyeoungwon Seo , Sungwon Yoo , Kyunghwan Lee
IPC: H01L29/66 , G11C11/39 , G11C11/402 , H01L29/749 , H01L27/102
CPC classification number: G11C11/4023 , G11C11/39 , H01L27/1027 , H01L29/66363 , H01L29/749
Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.
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公开(公告)号:US20240023340A1
公开(公告)日:2024-01-18
申请号:US18222278
申请日:2023-07-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Suhwan LIM , Yongseok Kim , Juhyung Kim , Minjun Lee
IPC: H10B51/30 , H10B51/10 , H10B51/40 , H10B80/00 , H01L25/065 , H10B43/10 , H10B43/27 , H10B43/40 , H10B43/35 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40
CPC classification number: H10B51/30 , H10B51/10 , H10B51/40 , H10B80/00 , H01L25/0652 , H10B43/10 , H10B43/27 , H10B43/40 , H10B43/35 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H01L2225/06506
Abstract: The present disclosure provides methods, apparatuses, and systems for operating and manufacturing a semiconductor device. In some embodiments, a semiconductor device includes a stack structure including interlayer insulating layers and gate electrodes, a channel layer disposed inside a hole penetrating through the stack structure, a data storage layer disposed between the stack structure and the channel layer, data storage patterns disposed between the data storage layer and the gate electrodes, and dielectric layers disposed between the data storage patterns and the gate electrodes. The interlayer insulating layers and the gate electrodes are alternately and repeatedly stacked in a first direction. A first material of the data storage layer is different from a second material of the data storage patterns.
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公开(公告)号:US20230371269A1
公开(公告)日:2023-11-16
申请号:US18195522
申请日:2023-05-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyuncheol Kim , Yongseok Kim , Kiheun Lee , Daewon Ha
CPC classification number: H10B51/30 , H01L29/40111 , H01L29/78391 , H10B51/10
Abstract: A memory device includes a channel region, a conductive electrode on the channel region, and a data storage structure between the channel region and the conductive electrode. The data storage structure includes a stack structure including two-dimensional material layers and ferroelectric layers stacked alternately and repeatedly in a direction perpendicular to a surface of the channel region. A thickness of each of the ferroelectric layers is greater than a thickness of each of the two-dimensional material layers.
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公开(公告)号:US20230309314A1
公开(公告)日:2023-09-28
申请号:US18108374
申请日:2023-02-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kyunghwan LEE , Yongseok Kim , Daewon Ha
CPC classification number: H10B51/20 , H10B51/10 , H01L29/516 , H01L29/78391
Abstract: A three-dimensional ferroelectric random access memory (3D FeRAM) device includes: a gate electrode extending in a vertical direction on a substrate; a ferroelectric pattern and a gate insulation pattern stacked on the gate electrode in a horizontal direction to surround the gate electrode; first and second channels spaced apart from each other in the horizontal direction on an outer sidewall of the gate insulation pattern; first source/drain pattern structures spaced apart from each other in the vertical direction on an outer sidewall of the first channel; and second source/drain pattern structures spaced apart from each other in the vertical direction on an outer sidewall of the second channel.
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公开(公告)号:US11659971B2
公开(公告)日:2023-05-30
申请号:US16891673
申请日:2020-06-03
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sinae Kim , Yongseok Kim , Minro Yun , Yeonkyu Jeong , Shin Kim , Jaeyoul Jeong
CPC classification number: A47L9/2836 , A47L9/009 , A47L9/2852 , A47L9/2889 , A47L2201/04
Abstract: Disclosed are a robot cleaner. The robot cleaner includes: a cleaner body configured to move in an area and clean the area; and a sensor assembly provided in the cleaner body. The sensor assembly includes: a main sensor configured to be moveable between a sensing position where the main sensor protrudes out of the cleaner body and a settled position where the main sensor is inside the cleaner body; a sensor position changer configured to allow the main sensor to move between the sensing position and the settled position; and a stopper configured to restrict the sensor position changer from allowing the main sensor at the sensing position to move towards the settled position.
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公开(公告)号:US20230163132A1
公开(公告)日:2023-05-25
申请号:US18098174
申请日:2023-01-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyuncheol Kim , Yongseok Kim , Huijung Kim , Satoru Yamada , Sungwon Yoo , Kyunghwan Lee , Jaeho Hong
IPC: H01L27/102 , H01L29/74
CPC classification number: H01L27/1027 , H01L29/742
Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.
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公开(公告)号:US20230075559A1
公开(公告)日:2023-03-09
申请号:US17741219
申请日:2022-05-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyuncheol Kim , Yongseok Kim , Dongsoo Woo , Kyunghwan Lee
IPC: H01L29/78 , H01L29/417 , H01L29/10
Abstract: A semiconductor device includes: a channel; a gate structure on the channel; a first source/drain arranged at a first end of the channel and including a metal; a first tunable band-gap layer arranged between the channel and the first source/drain and having a band gap that changes according to stress; a first electrostrictive layer between the gate structure and the first tunable band-gap layer, the first electrostrictive layer having a property of being deformed based on and upon application of an electric field; and a second source/drain at a second end of the channel.
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