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    Stacked integrated circuit device including multiple substrates and method of manufacturing the same
    51.
    发明申请
    Stacked integrated circuit device including multiple substrates and method of manufacturing the same 审中-公开
    包括多个基板的堆叠集成电路器件及其制造方法

    公开(公告)号：US20050110159A1

    公开(公告)日：2005-05-26

    申请号：US10977702

    申请日：2004-10-28

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L23/12 ,  H01L21/762 ,  H01L21/822 ,  H01L25/065 ,  H01L27/06 ,  H01L29/04

    CPC分类号： H01L21/76251 ,  H01L21/8221 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a stacked integrated circuit device including multiple substrates and a method of manufacturing the same. A first integrated circuit substrate, a first integrated circuit formed on the first integrated circuit substrate, and a first passivation insulating layer are sequentially formed. Then, wafer bonding technique for forming an SOI substrate is used, thereby forming a second integrated circuit substrate on the first passivation insulating layer. While forming a second integrated circuit on the second integrated circuit substrate, at least one device-connecting interconnect electrically connects the first and second Integrated circuits and penetrates the second integrated circuit substrate and the first passivation layer. A second passivation insulating layer is formed on an upper surface of the second integrated circuit.

    摘要翻译： 提供了包括多个基板的堆叠集成电路器件及其制造方法。 依次形成第一集成电路基板，形成在第一集成电路基板上的第一集成电路和第一钝化绝缘层。 然后，使用用于形成SOI衬底的晶片接合技术，从而在第一钝化绝缘层上形成第二集成电路衬底。 当在第二集成电路衬底上形成第二集成电路时，至少一个器件连接互连电连接第一和第二集成电路并且穿透第二集成电路衬底和第一钝化层。 第二钝化绝缘层形成在第二集成电路的上表面上。

    Methods of manufacturing charge trap-type non-volatile memory devices
    53.
    发明授权
    Methods of manufacturing charge trap-type non-volatile memory devices 有权
    制造电荷陷阱型非易失性存储器件的方法

    公开(公告)号：US08178408B2

    公开(公告)日：2012-05-15

    申请号：US12651781

    申请日：2010-01-04

    申请人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

    发明人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

    IPC分类号： H01L21/336 ,  H01L21/3205

    CPC分类号： H01L27/11568

    摘要： Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer.

    摘要翻译： 一些方法涉及制造电荷陷阱型非易失性存储器件。 可以形成在衬底中沿第一方向延伸的隔离层图案。 通过使邻近隔离层图案的基板的暴露表面凹陷而在基板中形成凹部单元。 隧道绝缘层和电荷陷阱层依次形成在基板上。 图案化隧道绝缘层和电荷陷阱层，通过蚀刻衬底的限定区域，隔离层图案，隧道绝缘层，隔离层状图案，隔离层状图案，隧道绝缘层， 并且电荷陷阱层直到设置在凹陷单元的底表面上的电荷陷阱层的顶表面与隔离层图案的顶表面对准。 形成了覆盖电荷陷阱层图案，隔离层图案和插入在电荷阱图案之间的基板的限定区域的阻挡绝缘层。 在阻挡绝缘层上形成面对电荷陷阱层图案的栅电极图案。 该制造过程可以减小单元存储单元之间的电荷扩展和/或可以防止/避免阻塞绝缘层的击穿电压的降低。

    Semiconductor devices having a field effect transistor and methods of fabricating the same
    57.
    发明授权
    Semiconductor devices having a field effect transistor and methods of fabricating the same 有权
    具有场效应晶体管的半导体器件及其制造方法

    公开(公告)号：US07510932B2

    公开(公告)日：2009-03-31

    申请号：US11764751

    申请日：2007-06-18

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78687 ,  Y10S438/933

    摘要： A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.

    摘要翻译： 提供具有场效应晶体管的半导体器件及其形成方法。 半导体器件优选地包括设置在衬底的预定区域上的器件有源图案。 栅电极优选地跨过器件有源图案，由栅极绝缘层插入。 支撑图案优选地插入在器件活性图案和基底之间。 支撑图案可以设置在栅电极下方。 填充绝缘图案优选地设置在装置活性图案和填充绝缘图案之间。 填充绝缘图案可以设置在源极/漏极区域下方。 栅电极下方的器件有源图案优选由具有比硅晶格宽的晶格宽度的应变硅形成。

    Metal oxide semiconductor (MOS) transistors having three dimensional channels
    58.
    发明授权
    Metal oxide semiconductor (MOS) transistors having three dimensional channels 有权
    具有三维通道的金属氧化物半导体（MOS）晶体管

    公开(公告)号：US07473963B2

    公开(公告)日：2009-01-06

    申请号：US11854734

    申请日：2007-09-13

    申请人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    发明人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7842

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

    摘要翻译： 金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。 第一和第二沟道区设置在源区和漏区之间。 沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。 第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。 在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

    Semiconductor device employing buried insulating layer and method of fabricating the same
    60.
    发明授权
    Semiconductor device employing buried insulating layer and method of fabricating the same 有权
    采用埋层绝缘层的半导体器件及其制造方法

    公开(公告)号：US07321144B2

    公开(公告)日：2008-01-22

    申请号：US11011258

    申请日：2004-12-13

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L29/66651 ,  H01L27/10873 ,  H01L29/0653 ,  H01L29/66659

    摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

    摘要翻译： 半导体器件采用非对称埋层绝缘层及其制造方法。 半导体器件包括下半导体衬底。 上硅图案位于下半导体衬底上。 上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。 栅电极与上硅图案电绝缘，并且在沟道区域上相交。 位线和单元电容器分别电连接到源极区域和漏极区域。 掩埋绝缘层插入在漏区和下半导体衬底之间。 掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。