公开(公告)号：US20060060860A1

公开(公告)日：2006-03-23

申请号：US11205311

申请日：2005-08-17

申请人： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi ,  Hideki Nemoto

发明人： Shunpei Yamazaki ,  Akira Mase ,  Masaaki Hiroki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Hideki Uochi ,  Hideki Nemoto

IPC分类号： H01L29/04

CPC分类号： H01L27/1222 ,  G02F1/1368 ,  G02F2001/136245 ,  G09G2300/0823 ,  H01L27/1214 ,  H01L27/1248 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78618 ,  H04N3/127

摘要： An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

公开(公告)号：US20060060852A1

公开(公告)日：2006-03-23

申请号：US11206293

申请日：2005-08-18

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Akira Mase ,  Hideki Uochi

IPC分类号： H01L29/04 ,  H01L21/84

CPC分类号： H01L29/66757 ,  H01L27/1255

摘要： A thin-film semiconductor device or integrated circuit comprising an insulating substrate, TFTs (thin-film transistors) formed on the substrate, and multilayer conductive interconnections. The circuit has a first metallization layer becoming gate electrodes and gate interconnections. The surface of the first metallization layer is oxidized by anodic oxidation to form an insulating coating on the surface of the first metallization layer. A second metallization layer becoming source and drain electrodes or conductive interconnections is then formed on the insulating coating directly or via an interlayer insulator. An improvement in the production yield and improved reliability are accomplished.

摘要翻译： 包括绝缘基板，形成在基板上的TFT（薄膜晶体管）和多层导电互连的薄膜半导体器件或集成电路。 该电路具有成为栅电极和栅极互连的第一金属化层。 通过阳极氧化将第一金属化层的表面氧化，以在第一金属化层的表面上形成绝缘涂层。 然后在绝缘涂层上直接或经由层间绝缘体形成成为源极和漏电极或导电互连的第二金属化层。 实现了产量的提高和可靠性的提高。

公开(公告)号：US06451638B1

公开(公告)日：2002-09-17

申请号：US09640078

申请日：2000-08-17

申请人： Hongyong Zhang ,  Hideki Uochi ,  Toru Takayama ,  Shunpei Yamazaki ,  Yasuhiko Takemura

发明人： Hongyong Zhang ,  Hideki Uochi ,  Toru Takayama ,  Shunpei Yamazaki ,  Yasuhiko Takemura

IPC分类号： H01L2184

CPC分类号： H01L21/02672 ,  H01L21/02532 ,  H01L21/2022 ,  H01L27/1281 ,  H01L29/66757

摘要： A process for fabricating a semiconductor by crystallizing a silicon film in a substantially amorphous state by annealing it at a temperature not higher than the crystallization temperature of amorphous silicon, and it comprises forming selectively, on the surface or under an amorphous silicon film, a coating, particles, clusters, and the like containing nickel, iron, cobalt, platinum or palladium either as a pure metal or a compound thereof such as a silicide, a salt, and the like, shaped into island-like portions, linear portions, stripes, or dots; and then annealing the resulting structure at a temperature lower than the crystallization temperature of an amorphous silicon by 20 to 150° C.

摘要翻译： 一种通过在不高于非晶硅的结晶温度的温度下进行退火将基本无定形态的硅膜结晶化的半导体制造方法，其包括在表面上或非晶硅膜下选择性地形成涂层 ，含有镍，铁，钴，铂或钯的颗粒，簇等作为纯金属或其化合物，例如硅化物，盐等，成形为岛状部分，线状部分，条纹 ，或点; 然后在低于非晶硅的结晶温度的温度下将所得结构退火20〜150℃。

公开(公告)号：US06396078B1

公开(公告)日：2002-05-28

申请号：US08666104

申请日：1996-06-19

申请人： Hideki Uochi ,  Masahiko Hayakawa ,  Mitsunori Sakama ,  Toshimitsu Konuma ,  Shunpei Yamazaki

发明人： Hideki Uochi ,  Masahiko Hayakawa ,  Mitsunori Sakama ,  Toshimitsu Konuma ,  Shunpei Yamazaki

IPC分类号： H01L2976

CPC分类号： H01L29/66757 ,  H01L21/76804 ,  H01L23/5283 ,  H01L23/5329 ,  H01L29/41733 ,  H01L29/42384 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having an improved contact hole through an interlayer insulator. A first insulating film comprising silicon nitride is deposited. A second insulating film comprising silicon oxide is deposited on the first insulating film. The deposition condition of the second insulating film is varied during the deposition so that the etching rate of the second insulating film increases from a lower portion toward an upper portion. Thereby, a contact hole which is formed by etching through the first and second insulating films has a tapered configuration to improve a reliability of a connection made therein.

公开(公告)号：US6084247A

公开(公告)日：2000-07-04

申请号：US769114

申请日：1996-12-18

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Toru Takayama ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Toru Takayama ,  Hideki Uochi

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/786 ,  H01L29/76 ,  H01L31/036

CPC分类号： H01L29/78696 ,  H01L21/2022 ,  H01L21/2026 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/78618

摘要： Semiconductor devices such as thin-film transistors formed by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.

摘要翻译： 半导体器件如薄膜晶体管，其通过在低于非晶硅的正常结晶温度或低于衬底的玻璃化转变温度的温度下退火基本非晶硅膜而形成，以使硅膜结晶。 镍，铁，钴或铂的岛，条纹，线或点，镍，铁，钴或铂的硅化物，乙酸盐或硝酸盐，含有各种盐，包含至少一种镍， 铁，钴和铂用作结晶的起始原料。 这些材料形成在非晶硅膜上或下方。

公开(公告)号：US5899709A

公开(公告)日：1999-05-04

申请号：US627083

申请日：1996-04-03

申请人： Shunpei Yamazaki ,  Hongyong Zhang ,  Hideki Uochi ,  Hiroki Adachi ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Hongyong Zhang ,  Hideki Uochi ,  Hiroki Adachi ,  Yasuhiko Takemura

IPC分类号： H01L21/321 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/49 ,  H01L21/28 ,  H01L21/283

CPC分类号： H01L27/1214 ,  H01L21/32105 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/66765

摘要： An improved method for manufacturing an insulated gate field effect transistor is described. The method comprises the steps of forming a semiconductor film on an insulating substrate, forming a gate insulating film on said semiconductor film, forming a gate electrode on said gate insulating film with said gate insulating film inbetween, anoding said gate electrode in order to coat an external surface of said gate electrode with an oxide film thereof and applying a negative or positive voltage to said gate electrode with respect to said semiconductor film. Lattice defects and interfacial states caused by the application of a positive voltage during the anoding are effectively eliminated by the negative voltage application.

摘要翻译： 描述了用于制造绝缘栅场效应晶体管的改进方法。 该方法包括以下步骤：在绝缘基板上形成半导体膜，在所述半导体膜上形成栅极绝缘膜，在所述栅极绝缘膜上形成栅电极，在其间具有栅极绝缘膜，对所述栅极电极进行涂覆 所述栅电极的外表面具有氧化膜，并相对于所述半导体膜向所述栅电极施加负电压或正电压。 通过施加负电压，能够有效地消除由于在安装期间施加正电压引起的晶格缺陷和界面状态。

公开(公告)号：US5897347A

公开(公告)日：1999-04-27

申请号：US718895

申请日：1996-09-24

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Toru Takayama ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Toru Takayama ,  Hideki Uochi

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/786 ,  H01L21/00 ,  H01L21/322

CPC分类号： H01L29/78696 ,  H01L21/2022 ,  H01L21/2026 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/78618

摘要： Method of fabricating semiconductor devices such as thin-film transistors by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.

摘要翻译： 通过在低于非晶硅的正常结晶温度或低于基板的玻璃化转变点的温度下退火基本非晶硅膜以使硅膜结晶的方法来制造诸如薄膜晶体管的半导体器件。 镍，铁，钴，铂，镍，铁，钴或铂的镍，铁钴或铂，硅化物，乙酸盐或硝酸盐的岛，条纹，线或点，含有各种盐，含有镍，铁， ，钴和铂用作结晶的起始材料。 这些材料形成在非晶硅膜上或下方。

公开(公告)号：US5879977A

公开(公告)日：1999-03-09

申请号：US636819

申请日：1996-04-23

申请人： Hongyong Zhang ,  Hideki Uochi ,  Toru Takayama ,  Shunpei Yamazaki ,  Yasuhiko Takemura

发明人： Hongyong Zhang ,  Hideki Uochi ,  Toru Takayama ,  Shunpei Yamazaki ,  Yasuhiko Takemura

IPC分类号： H01L21/20 ,  H01L21/00 ,  H01L21/324 ,  H01L21/336 ,  H01L27/12 ,  H01L29/02 ,  H01L29/78 ,  H01L29/786 ,  H01L21/10

CPC分类号： H01L21/2022 ,  H01L27/1281 ,  H01L29/66757

摘要： A process for fabricating a semiconductor by crystallizing a silicon film in a substantially amorphous state by annealing it at a temperature not higher than the crystallization temperature of amorphous silicon, and it comprises forming selectively, on the surface or under an amorphous silicon film, a coating, particles, clusters, and the like containing nickel, iron, cobalt, platinum or palladium either as a pure metal or a compound thereof such as a silicide, a salt, and the like, shaped into island-like portions, linear portions, stripes, or dots; and then annealing the resulting structure at a temperature lower than the crystallization temperature of an amorphous silicon by 20.degree. to 150.degree. C.

摘要翻译： 一种通过在不高于非晶硅的结晶温度的温度下进行退火将基本无定形态的硅膜结晶化的半导体制造方法，其包括在表面上或非晶硅膜下选择性地形成涂层 ，含有镍，铁，钴，铂或钯的颗粒，簇等作为纯金属或其化合物，例如硅化物，盐等，成形为岛状部分，线状部分，条纹 ，或点; 然后在低于非晶硅的结晶温度的温度下将所得结构退火20〜150℃。

公开(公告)号：US5830786A

公开(公告)日：1998-11-03

申请号：US654030

申请日：1996-05-28

申请人： Hongyong Zhang ,  Hideki Uochi ,  Shunpei Yamazaki ,  Yasuhiko Takemura ,  Minoru Miyazaki ,  Akane Murakami ,  Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara

发明人： Hongyong Zhang ,  Hideki Uochi ,  Shunpei Yamazaki ,  Yasuhiko Takemura ,  Minoru Miyazaki ,  Akane Murakami ,  Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/76 ,  H01L29/49 ,  H01L21/3215

CPC分类号： H01L21/02071 ,  H01L21/28079 ,  H01L21/32134 ,  H01L29/4908 ,  H01L29/66757

摘要： A process for fabricating an electronic circuit by oxidizing the surroundings of a metallic interconnection such as of aluminum, tantalum, and titanium, wherein anodic oxidation is effected at a temperature not higher than room temperature, preferably, at 10.degree. C. or lower, and more preferably, at 0.degree. C. or lower. The surface oxidation rate of a metallic interconnection can be maintained constant to provide a surface free of irregularities.

摘要翻译： 通过氧化诸如铝，钽和钛的金属互连的周围来制造电子电路的方法，其中阳极氧化在不高于室温，优选在10℃或更低的温度下进行，以及 更优选在0℃以下。 金属互连的表面氧化速率可以保持恒定，以提供没有凹凸的表面。

公开(公告)号：US5639698A

公开(公告)日：1997-06-17

申请号：US196856

申请日：1994-02-15

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Toru Takayama ,  Hideki Uochi

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura ,  Hongyong Zhang ,  Toru Takayama ,  Hideki Uochi

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L21/2022 ,  H01L21/2026 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/78618

摘要： Method of fabricating semiconductor devices such as thin-film transistors by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.

摘要翻译： 通过在低于非晶硅的正常结晶温度或低于基板的玻璃化转变点的温度下退火基本非晶硅膜以使硅膜结晶的方法来制造诸如薄膜晶体管的半导体器件。 镍，铁，钴或铂的岛，条纹，线或点，镍，铁，钴或铂的硅化物，乙酸盐或硝酸盐，含有各种盐，包含至少一种镍， 铁，钴和铂用作结晶的起始原料。 这些材料形成在非晶硅膜上或下方。