公开(公告)号：US5830786A

公开(公告)日：1998-11-03

申请号：US654030

申请日：1996-05-28

申请人： Hongyong Zhang ,  Hideki Uochi ,  Shunpei Yamazaki ,  Yasuhiko Takemura ,  Minoru Miyazaki ,  Akane Murakami ,  Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara

发明人： Hongyong Zhang ,  Hideki Uochi ,  Shunpei Yamazaki ,  Yasuhiko Takemura ,  Minoru Miyazaki ,  Akane Murakami ,  Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/76 ,  H01L29/49 ,  H01L21/3215

CPC分类号： H01L21/02071 ,  H01L21/28079 ,  H01L21/32134 ,  H01L29/4908 ,  H01L29/66757

摘要： A process for fabricating an electronic circuit by oxidizing the surroundings of a metallic interconnection such as of aluminum, tantalum, and titanium, wherein anodic oxidation is effected at a temperature not higher than room temperature, preferably, at 10.degree. C. or lower, and more preferably, at 0.degree. C. or lower. The surface oxidation rate of a metallic interconnection can be maintained constant to provide a surface free of irregularities.

摘要翻译： 通过氧化诸如铝，钽和钛的金属互连的周围来制造电子电路的方法，其中阳极氧化在不高于室温，优选在10℃或更低的温度下进行，以及 更优选在0℃以下。 金属互连的表面氧化速率可以保持恒定，以提供没有凹凸的表面。

公开(公告)号：US5580800A

公开(公告)日：1996-12-03

申请号：US213060

申请日：1994-03-15

申请人： Hongyong Zhang ,  Yasuhiko Takemura ,  Hideki Uochi ,  Itaru Koyama ,  Minoru Miyazaki ,  Akane Murakami ,  Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara

发明人： Hongyong Zhang ,  Yasuhiko Takemura ,  Hideki Uochi ,  Itaru Koyama ,  Minoru Miyazaki ,  Akane Murakami ,  Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/49 ,  H01L21/306

CPC分类号： H01L21/02071 ,  H01L21/28079 ,  H01L21/32134 ,  H01L29/4908 ,  H01L29/66757 ,  Y10S148/051

摘要： A thin film transistor according to this invention has a gate electrode comprising a lower layer of aluminum of a high purity of over 99.5% and an upper layer of aluminum containing over 0.5% silicon. Alternatively, it has a gate electrode made by adding a IIIa group element to a IIIb group element. Residues produced by the etching of the silicon-containing aluminum gate electrode are etched with a mixture solution of hydrofluoric acid, nitric acid and acetic acid. After contact holes have been formed in an interlayer insulating film, laser annealing is carried out, and metal electrodes are formed in the contact holes thereafter.

摘要翻译： 根据本发明的薄膜晶体管具有包括高纯度超过99.5％的低铝层的下电极和含有超过0.5％硅的上层铝的栅电极。 或者，其具有通过将IIIa族元素添加到IIIb族元素而制成的栅电极。 通过蚀刻含硅铝栅电极产生的残留物用氢氟酸，硝酸和乙酸的混合溶液进行蚀刻。 在层间绝缘膜中形成接触孔之后，进行激光退火，此后在接触孔中形成金属电极。

公开(公告)号：US20090289254A1

公开(公告)日：2009-11-26

申请号：US12534382

申请日：2009-08-03

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L29/786 ,  H01L29/04 ,  H01L27/12

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

摘要翻译： 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。

公开(公告)号：US07381599B2

公开(公告)日：2008-06-03

申请号：US11064821

申请日：2005-02-25

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L21/336

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

摘要翻译： 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。

公开(公告)号：US08198683B2

公开(公告)日：2012-06-12

申请号：US12958739

申请日：2010-12-02

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L29/786

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

摘要翻译： 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。

公开(公告)号：US07847355B2

公开(公告)日：2010-12-07

申请号：US12534382

申请日：2009-08-03

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L29/786

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

摘要翻译： 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。

公开(公告)号：US07525158B2

公开(公告)日：2009-04-28

申请号：US10893889

申请日：2004-07-20

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L29/786

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

摘要翻译： 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。

公开(公告)号：US06867431B2

公开(公告)日：2005-03-15

申请号：US08307167

申请日：1994-09-16

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L21/311 ,  H01L21/316 ,  H01L21/321 ,  H01L21/336 ,  H01L27/12 ,  H01L29/45 ,  H01L29/786 ,  H01L31/036 ,  H01L31/0368 ,  H01L31/0392

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

公开(公告)号：US20050142705A1

公开(公告)日：2005-06-30

申请号：US11064821

申请日：2005-02-25

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L21/311 ,  H01L21/316 ,  H01L21/321 ,  H01L21/336 ,  H01L27/12 ,  H01L29/45 ,  H01L29/786 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

公开(公告)号：US07569856B2

公开(公告)日：2009-08-04

申请号：US11078440

申请日：2005-03-14

申请人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

发明人： Toshimitsu Konuma ,  Akira Sugawara ,  Yukiko Uehara ,  Hongyong Zhang ,  Atsunori Suzuki ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Hideomi Suzawa ,  Hideki Uochi ,  Yasuhiko Takemura

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/84

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

摘要翻译： 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。