公开(公告)号：US5384789A

公开(公告)日：1995-01-24

申请号：US12644

申请日：1993-02-03

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  H01L27/10

CPC分类号： G06F11/1008 ,  G06F11/1076

摘要： A semiconductor memory device has a cell and amplifier portion, a syndrome generation circuit, an error checking and correction circuit, and a plurality of memory control blocks. The cell and amplifier portion has a memory cell array, a sense amplifier array, and a column gate array, and each of the memory control blocks has a data bus amplifier, a write amplifier, and a syndrome decoder circuit which decodes syndrome output from the syndrome generation circuit. Consequently, an occupancy area can be reduced by decreasing the number of wiring lines, and a large scale integration and a low power consumption can be realized.

摘要翻译： 半导体存储器件具有单元和放大器部分，校正子产生电路，错误校验和校正电路以及多个存储器控制块。 单元和放大器部分具有存储单元阵列，读出放大器阵列和列门阵列，并且每个存储器控制块具有数据总线放大器，写入放大器和校正子解码器电路，其对来自 综合征发生电路。 因此，可以通过减少布线数量来减少占用面积，并且可以实现大规模集成和低功耗。

公开(公告)号：US08027220B2

公开(公告)日：2011-09-27

申请号：US12147061

申请日：2008-06-26

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C8/00

CPC分类号： G11C11/406 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012 ,  G11C2211/4061

摘要： An oscillation device includes a first setting unit that outputs an oscillation period designation signal, a calculating unit that performs an arithmetic operation on the oscillation period designation signal, and an oscillating unit that generates an oscillation signal having a period based on the oscillation period designation signal subjected to the arithmetic operation.

摘要翻译： 振荡装置包括：输出振荡周期指定信号的第一设定单元，对振荡周期指定信号进行算术运算的运算单元;以及产生基于振荡周期指定信号的周期的振荡信号的振荡单元 进行算术运算。

公开(公告)号：US20100214823A1

公开(公告)日：2010-08-26

申请号：US12707044

申请日：2010-02-17

申请人： Hiroyuki Ogawa ,  Hiroyoshi Tomita ,  Masato Takita

发明人： Hiroyuki Ogawa ,  Hiroyoshi Tomita ,  Masato Takita

IPC分类号： G11C11/24 ,  H01L21/8242 ,  G11C11/34

CPC分类号： H01L27/0207 ,  G11C5/063 ,  G11C7/02 ,  G11C7/18 ,  G11C11/4097 ,  H01L27/1085 ,  H01L27/10885 ,  H01L27/10897

摘要： A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer.

摘要翻译： 半导体器件包括半导体衬底; 存储单元阵列，包括形成在所述半导体衬底上的多个存储单元，并且在所述半导体衬底的表面上沿第一方向和第二方向布置成矩阵; 多个读出放大器，形成在半导体衬底上并包括第一读出放大器和第二读出放大器; 以及沿着存储单元阵列上方的第一方向延伸并沿第二方向并排布置的多个位线，其中多个位线包括形成在第一布线层中的第一位线对和第二位线 形成在位于第一布线层上方的第二布线层中。

公开(公告)号：US07646660B2

公开(公告)日：2010-01-12

申请号：US12035248

申请日：2008-02-21

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40622 ,  G11C2211/4061

摘要： Partial refresh information indicating enabling/disabling of a refresh operation is set according to an external input and is output as a partial set signal. A refresh request signal is output periodically corresponding to a memory block for which a refresh operation is enabled. The partial set signal is masked so as to enable a refresh operation for all of the memory blocks during a period in which the partial refresh information is changed by the external input. Thus, it is possible to prevent disabling of a refresh operation in response to a refresh request even when timing of changing the partial refresh information and timing of occurrence of the refresh request signal overlap. Consequently, the refresh operation can be executed securely, and malfunctioning of the semiconductor memory can be prevented.

摘要翻译： 根据外部输入设定表示刷新动作的启用/禁止的部分刷新信息，作为部分设定信号输出。 周期性地对与启用刷新操作的存储器块相对应地输出刷新请求信号。 部分设置信号被屏蔽，以便在通过外部输入改变部分刷新信息的时段期间使得能够对所有存储器块进行刷新操作。 因此，即使当改变部分刷新信息的定时和刷新请求信号的发生定时重叠时，也可以防止响应于刷新请求而禁止刷新操作。 因此，可以可靠地执行刷新操作，并且可以防止半导体存储器的故障。

公开(公告)号：US07633818B2

公开(公告)日：2009-12-15

申请号：US11892358

申请日：2007-08-22

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/026

摘要： The present invention detects a sense amplifier having an unbalanced characteristic. In a test method for a semiconductor memory device for detecting a sense amplifier having an unbalanced characteristic, an intermediate potential having different H and L levels from normal operation is restored in a first memory cell of a first bit line connected to a test target sense amplifier, charge quantity when the capacitance of the capacitor is small is virtually stored in the first memory cell, then the data of the first memory cell is read, and a malfunction of the sense amplifier is checked based on the presence of an error of read data.

摘要翻译： 本发明检测具有不平衡特性的读出放大器。 在用于检测具有不平衡特性的读出放大器的半导体存储器件的测试方法中，在连接到测试目标读出放大器的第一位线的第一存储单元中恢复与正常操作不同的H和L电平的中间电位 ，当电容器的电容小时的电荷量实际上被存储在第一存储单元中，然后读取第一存储单元的数据，并且基于读数据的错误的存在来检查读出放大器的故障 。

公开(公告)号：US20080080286A1

公开(公告)日：2008-04-03

申请号：US11892497

申请日：2007-08-23

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/406 ,  G11C5/143 ,  G11C7/1045 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4074

摘要： A semiconductor memory device includes a timing signal circuit to generate a refresh timing signal comprised of a series of pulses, a refresh address circuit to generate a refresh address in synchronization with each pulse of the refresh timing signal, a pulse selecting circuit to assert a refresh request signal in synchronization with pulses selected from the series of pulses, and a memory core to receive the refresh address and the refresh request signal and to perform a refresh operation with respect to the refresh address in response to assertion of the refresh request signal, wherein arrangement is made to switch between a first operation mode in which the selected pulses are obtained by selecting one pulse out of every predetermined number of pulses from the series of pulses and a second operation mode in which the selected pulses are obtained by selecting consecutive pulses from the series of pulses.

摘要翻译： 半导体存储器件包括：定时信号电路，用于产生由一系列脉冲组成的刷新定时信号;刷新地址电路，用于与刷新定时信号的每个脉冲同步产生刷新地址;脉冲选择电路，用于断言刷新 请求信号与从一系列脉冲中选择的脉冲同步;以及存储器核，用于接收刷新地址和刷新请求信号，并响应于刷新请求信号的断言而对刷新地址执行刷新操作，其中 通过从脉冲串中选出每一个预定数量的脉冲中的一个脉冲和第二操作模式，在第一操作模式和第二操作模式之间切换选择的脉冲的第一操作模式，其中通过从 一系列脉冲。

公开(公告)号：US07323789B2

公开(公告)日：2008-01-29

申请号：US11043993

申请日：2005-01-28

申请人： Fusao Seki ,  Tatsushi Otsuka ,  Masanori Kurita ,  Shinnosuke Kamata ,  Toshiya Uchida ,  Hiroyoshi Tomita ,  Hiroyuki Kobayashi

发明人： Fusao Seki ,  Tatsushi Otsuka ,  Masanori Kurita ,  Shinnosuke Kamata ,  Toshiya Uchida ,  Hiroyoshi Tomita ,  Hiroyuki Kobayashi

IPC分类号： G11C8/00

CPC分类号： G11C5/04 ,  G11C5/063 ,  H01L2224/49113 ,  H01L2924/3011 ,  H01L2924/00

摘要： A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.

摘要翻译： 时钟输出板和返回时钟接收焊盘设置在集成电路芯片的靠近侧面的部分和与集成电路芯片的与侧面相反的另一侧的部分的逻辑芯片上。 时钟接收垫分别在靠近侧面和另一侧的部分设置在存储器芯片上。 时钟接收板电连接到时钟输出板和返回时钟接收板。 多个时钟信号从逻辑芯片提供给存储器芯片，并且多个返回时钟信号从存储器芯片返回到逻辑芯片。

公开(公告)号：US20050180242A1

公开(公告)日：2005-08-18

申请号：US11103551

申请日：2005-04-12

申请人： Hiroyoshi Tomita ,  Toshiya Uchida

发明人： Hiroyoshi Tomita ,  Toshiya Uchida

IPC分类号： G11C7/12 ,  G11C11/406 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/406 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2211/4065

摘要： A semiconductor storage device has a memory cell (501, 502) storing data; bit lines (BL1, BL2) connected to the memory cell, allowing therethrough data input or output to or from the memory cell; a sense amplifier (506a) connected to said bit lines, amplifying data on the bit lines; and a switching transistor (505a) connecting or disconnecting the bit line connected to the memory cell to or from the bit line connected to the sense amplifier. The switching transistor operates differently in a first memory cell access operation and in a second memory cell access operation.

摘要翻译： 半导体存储装置具有存储数据的存储单元（501,502） 连接到存储单元的位线（BL 1，BL 2），允许数据输入或输出到存储单元; 连接到所述位线的读出放大器（506a），放大位线上的数据; 以及开关晶体管（505a），连接或断开与连接到读出放大器的位线连接到存储单元的位线。 开关晶体管在第一存储器单元存取操作和第二存储单元存取操作中的操作方式不同。

公开(公告)号：US06813696B2

公开(公告)日：2004-11-02

申请号：US10694982

申请日：2003-10-29

申请人： Tatsuya Kanda ,  Hiroyoshi Tomita

发明人： Tatsuya Kanda ,  Hiroyoshi Tomita

IPC分类号： G06F1200

CPC分类号： G11C7/1087 ,  G11C7/1021 ,  G11C7/1039 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/222 ,  G11C29/14

摘要： The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional memory test equipment having a transfer type which transfers the data in synchronization with the rising and falling edges of the external clock. The semiconductor memory device has a write amplifier control section 14 and I/O data buffer/register 22 as a data transfer circuit corresponding to the data transfer type for the DDR type and SDR type. Also, a mode register 28 is formed to be used as a switch signal to switch the data transfer circuit to either DDR type or SDR type.

摘要翻译： 本发明涉及一种与外部时钟同步写入或读取数据的SDRAM及其控制方法，其目的在于提供一种半导体存储器件及其方法，该半导体存储器件及其方法可以容易地由具有 传输类型与外部时钟的上升沿和下降沿同步传输数据。 半导体存储器件具有写入放大器控制部分14和I / O数据缓冲器/寄存器22，作为对应于DDR类型和SDR类型的数据传输类型的数据传输电路。 此外，模式寄存器28形成为用作切换信号以将数据传输电路切换为DDR类型或SDR类型。

公开(公告)号：US06510095B1

公开(公告)日：2003-01-21

申请号：US10073231

申请日：2002-02-13

申请人： Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Masao Taguchi

发明人： Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Masao Taguchi

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/2227

摘要： A command receiver circuit receives a command signal in synchronization with either a rising edge or a falling edge of a clock signal. A data input/output circuit starts an output of read data and an input of write data in synchronization with the edges of the clock signal which are set in response to reception timing of the command signal. Since the command signal can be received in synchronization with both edges of the clock signal, it is possible to halve a clock cycle when a reception rate is the same as that of the conventional art. As a result of this, in a system on which the semiconductor memory device is mounted, it is possible to halve the frequency of a system clock and to reduce power consumption of a clock synchronization circuit in the system, without reducing a data input/output rate for the semiconductor memory device.

摘要翻译： 命令接收器电路与时钟信号的上升沿或下降沿同步地接收命令信号。 数据输入/输出电路与响应命令信号的接收定时而设置的时钟信号的边沿同步地开始读取数据的输出和写入数据的输入。 由于可以与时钟信号的两个边沿同步地接收命令信号，所以当接收速率与传统技术的接收速率相同时，可以将时钟周期减半。 结果，在安装了半导体存储器件的系统中，可以将系统时钟的频率减半，并且可以降低系统中时钟同步电路的功耗，而不减少数据输入/输出 速率为半导体存储器件。