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公开(公告)号：US20150003166A1
公开(公告)日：2015-01-01
申请号：US14449926
申请日：2014-08-01
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Thuan Vu
IPC: G11C16/10 , G11C16/26 , H01L27/115
CPC classification number: G11C16/10 , G11C7/00 , G11C7/22 , G11C16/26 , G11C16/28 , G11C2207/2263 , G11C2211/5647 , H01L27/11517
Abstract: A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.
Abstract translation: 非易失性存储器件具有用于提供编程电流和非易失性存储器单元阵列的电荷泵。 阵列的每个存储单元都由来自电荷泵的编程电流编程。 非易失性存储器单元的阵列被分割成多个单元，每个单元包括多个存储器单元。 指示器存储单元与每单位的非易失性存储单元相关联。 编程电路使用编程电流来对每个单元的存储器单元进行编程，当每个单元的存储单元的百分之五十或更少被编程时，编程每个单元的存储器单元的反相和与 每个单元使用编程电流时，每个单元的存储单元的百分之五十以上将被编程。
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52.发明申请公开(公告)号：US20140269049A1
公开(公告)日：2014-09-18
申请号：US13958410
申请日：2013-08-02
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
Abstract: A hybrid charge pump and control circuit for use in a memory device is disclosed.
Abstract translation: 公开了一种用于存储器件的混合电荷泵和控制电路。
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公开(公告)号：US11849577B2
公开(公告)日：2023-12-19
申请号：US17845782
申请日：2022-06-21
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Hung Quoc Nguyen , Nhan Do
IPC: G11C16/04 , H10B41/40 , G11C16/14 , G11C16/26 , H01L29/423 , H01L29/788 , H10B41/10 , H10B41/30
CPC classification number: H10B41/40 , G11C16/0408 , G11C16/14 , G11C16/26 , H01L29/42328 , H01L29/7881 , H10B41/10 , H10B41/30
Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.
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公开(公告)号：US20210210144A9
公开(公告)日：2021-07-08
申请号：US16574059
申请日：2019-09-17
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.
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公开(公告)号：US20210175240A1
公开(公告)日：2021-06-10
申请号：US17178520
申请日：2021-02-18
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Hung Quoc Nguyen , Nhan Do
IPC: H01L27/11526 , H01L27/11519 , H01L27/11521 , G11C16/04 , G11C16/14 , G11C16/26 , H01L29/423 , H01L29/788
Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.
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Patent Agency Ranking
公开(公告)号：US10373686B2
公开(公告)日：2019-08-06
申请号：US15660552
申请日：2017-07-26
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
Abstract: A three-dimensional flash memory system is disclosed. The system comprises a memory array comprising a plurality of stacked dies, where each die comprises memory cells. The system further comprises a plurality of pins, where the function of at least some of the pins can be configured using a mechanism that selects a function for those pins from a plurality of possible functions.
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公开(公告)号：US10297327B2
公开(公告)日：2019-05-21
申请号：US15952155
申请日：2018-04-12
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC: G11C16/26 , G11C16/14 , G11C16/08 , G11C7/06 , G11C8/08 , G11C16/10 , G11C16/28 , H01L27/112 , H01L27/11582 , H01L49/02
Abstract: The present invention relates to a flash memory system comprising one or more sense amplifiers for reading data stored in flash memory cells. The sense amplifiers utilize fully depleted silicon-on-insulator transistors to minimize leakage. The fully depleted silicon-on-insulator transistors comprise one or more fully depleted silicon-on-insulator NMOS transistors and/or one or more fully depleted silicon-on-insulator PMOS transistors.
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公开(公告)号：US20180047454A1
公开(公告)日：2018-02-15
申请号：US15792590
申请日：2017-10-24
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen , Vipin Tiwari
CPC classification number: G11C16/28 , G11C7/062 , G11C7/067 , G11C7/12 , G11C16/00 , G11C16/06 , G11C16/24 , G11C16/26 , G11C2207/063 , H01L27/11519
Abstract: Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.
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公开(公告)号：US20170358360A1
公开(公告)日：2017-12-14
申请号：US15687191
申请日：2017-08-25
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.
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公开(公告)号：US20170323682A1
公开(公告)日：2017-11-09
申请号：US15660552
申请日：2017-07-26
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
CPC classification number: G11C16/08 , G11C7/1045 , G11C7/1057 , G11C16/04 , G11C2207/105 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/1435 , H01L2924/1438 , H01L2924/15311 , H01L2924/157
Abstract: A three-dimensional flash memory system is disclosed. The system comprises a memory array comprising a plurality of stacked dies, where each die comprises memory cells. The system further comprises a plurality of pins, where the function of at least some of the pins can be configured using a mechanism that selects a function for those pins from a plurality of possible functions.
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