公开(公告)号：US20220310630A1

公开(公告)日：2022-09-29

申请号：US17842208

申请日：2022-06-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Wei Wang ,  Lien Jung Hung ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Yu-Kuan Lin ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Choh Fei Yeap

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419 ,  H01L21/66 ,  H01L23/528 ,  H01L27/11524 ,  H04N21/426

Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.

公开(公告)号：US20200272781A1

公开(公告)日：2020-08-27

申请号：US16722865

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Ming Chang ,  Ruey-Wen Chang ,  Ping-Wei Wang ,  Sheng-Hsiung Wang ,  Chi-Yu Lu

IPC: G06F30/392 ,  H01L27/11 ,  G06F30/398 ,  H01L27/088

Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.

公开(公告)号：US10685704B2

公开(公告)日：2020-06-16

申请号：US16241717

申请日：2019-01-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Wu ,  Wei Min Chan ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Ping-Wei Wang

IPC: G11C11/40 ,  G11C11/419 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/41 ,  G11C11/412

Abstract: A static random access memory (SRAM) includes a bit cell that includes a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a write multiplexer connected to the bit information path. The write multiplexer includes a p-type transistor configured to selectively couple the bit information path to a flip-flop.

公开(公告)号：US10176864B2

公开(公告)日：2019-01-08

申请号：US15633167

申请日：2017-06-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Wu ,  Wei Min Chan ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Ping-Wei Wang

IPC: G11C11/40 ,  G11C11/419 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/41 ,  G11C11/412

Abstract: A static random access memory (SRAM) includes a bit cell that receives an operating voltage and a reference voltage, and includes a p-type pass gate. A bit information path is connected to the bit cell by the p-type pass gate, and a pre-discharge circuit is connected to the bit information path. The pre-discharge circuit includes an n-type transistor that discharges the bit information path to the reference voltage.

公开(公告)号：US09362399B2

公开(公告)日：2016-06-07

申请号：US14600847

申请日：2015-01-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng Chiang Hung ,  Huai-Ying Huang ,  Ping-Wei Wang

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/167 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L29/7836 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6659

Abstract: The present disclosure relates to methods for fabricating a field-effect transistor. The method includes performing a pocket implantation to a semiconductor substrate; thereafter forming a polysilicon layer on the semiconductor substrate; and patterning the polysilicon layer to form a polysilicon gate.The field-effect transistor (FET) includes a well of a first type dopant, formed in a semiconductor substrate; a metal gate disposed on the semiconductor substrate and overlying the well; a channel formed in the semiconductor substrate and underlying the metal gate; source and drain regions of a second type dopant opposite from the first type, the source and drain regions being formed in the semiconductor substrate and on opposite sides of the channel; and a pocket doping profile of the first type dopant and being defined in the well to form a continuous and uniform doping region from the source region to the drain region.

公开(公告)号：US20140254249A1

公开(公告)日：2014-09-11

申请号：US14285362

申请日：2014-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Huai-Ying Huang ,  Yu-Kuan Lin ,  Sheng Chiang Hung ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Ping-Wei Wang

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/419

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract translation: 描述SRAM单元和SRAM单元阵列。 在一个实施例中，SRAM单元包括与第一反相器交叉耦合的第一反相器和第二反相器，以形成第一数据存储节点和用于锁存值的互补的第二数据存储节点。 SRAM单元还包括第一栅极晶体管和开关晶体管。 第一栅极晶体管的第一源极/漏极耦合到第一数据存储节点，并且第一栅极晶体管的第二源极/漏极耦合到第一位线。 开关晶体管的第一源极/漏极耦合到第一通过栅极晶体管的栅极。

公开(公告)号：US08743579B2

公开(公告)日：2014-06-03

申请号：US13864873

申请日：2013-04-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Huai-Yang Huang ,  Yu-Kuan Lin ,  Sheng Chiang Hung ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Ping-Wei Wang

IPC: G11C15/00

CPC classification number: G11C11/412 ,  G11C11/419

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract translation: 描述SRAM单元和SRAM单元阵列。 在一个实施例中，SRAM单元包括与第一反相器交叉耦合的第一反相器和第二反相器，以形成第一数据存储节点和用于锁存值的互补的第二数据存储节点。 SRAM单元还包括第一栅极晶体管和开关晶体管。 第一栅极晶体管的第一源极/漏极耦合到第一数据存储节点，并且第一栅极晶体管的第二源极/漏极耦合到第一位线。 开关晶体管的第一源极/漏极耦合到第一通过栅极晶体管的栅极。

公开(公告)号：US20130250660A1

公开(公告)日：2013-09-26

申请号：US13864873

申请日：2013-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Huai-Ying Huang ,  Yu-Kuan Lin ,  Sheng Chiang Hung ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Ping-Wei Wang

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C11/419

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract translation: 描述SRAM单元和SRAM单元阵列。 在一个实施例中，SRAM单元包括与第一反相器交叉耦合的第一反相器和第二反相器，以形成第一数据存储节点和用于锁存值的互补的第二数据存储节点。 SRAM单元还包括第一栅极晶体管和开关晶体管。 第一栅极晶体管的第一源极/漏极耦合到第一数据存储节点，并且第一栅极晶体管的第二源极/漏极耦合到第一位线。 开关晶体管的第一源极/漏极耦合到第一通过栅极晶体管的栅极。

公开(公告)号：US20130146987A1

公开(公告)日：2013-06-13

申请号：US13710377

申请日：2012-12-10

Applicant: Taiwan Semiconductor Manufacturing Company, LTD

Inventor： Sheng Chiang Hung ,  Huai-Ying Huang ,  Ping-Wei Wang

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/11 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7848

Abstract: A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.

Abstract translation: 提供了具有金属栅极晶体管的SRAM器件。 SRAM器件在衬底上包括PMOS结构和NMOS结构。 PMOS和NMOS结构中的每一个包括p型金属功函数层和n型金属功函数层。 p型工作金属功能层和n型金属功函数层形成PMOS和NMOS结构的组合功函数。

公开(公告)号：US20250048686A1

公开(公告)日：2025-02-06

申请号：US18410195

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Wei Wang ,  Gu-Huan Li ,  Jui-Lin Chen

IPC: H01L29/06 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H10B20/25

Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a semiconductor substrate having a frontside and a backside; a shallow trench isolation (STI) structure formed in the semiconductor substrate and defining an active region, wherein the STI structure includes a STI bottom surface, wherein the semiconductor substrate includes a substrate bottom surface, and wherein the STI bottom surface and the substrate bottom surface are coplanar; a field-effect transistor (FET) over the active region and formed on the frontside of the semiconductor substrate; and a backside dielectric layer disposed on the substrate bottom surface and the STI bottom surface.