公开(公告)号：US20220336641A1

公开(公告)日：2022-10-20

申请号：US17811266

申请日：2022-07-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pei-Wei Wang ,  Chih-Chuan Yang ,  Yu-Kuan Lin ,  Choh Fei Yeap

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L23/00 ,  H01L27/11 ,  H01L29/78 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

摘要： A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.

公开(公告)号：US12080604B2

公开(公告)日：2024-09-03

申请号：US18362163

申请日：2023-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Wei Lee ,  Chien-Yuan Chen ,  Jo-Chun Hung ,  Yung-Hsiang Chan ,  Yu-Kuan Lin ,  Lien-Jung Hung

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/7851 ,  H01L29/78696

摘要： A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

公开(公告)号：US12080602B2

公开(公告)日：2024-09-03

申请号：US18331326

申请日：2023-06-08

申请人： Taiwan Semiconductor Manufacturing Company., Ltd.

发明人： Wen-Chun Keng ,  Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/08

CPC分类号： H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0847

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first fin structure and a second fin structure over the substrate. A top surface of the first fin structure and a top surface of the second fin structure are at different height levels. The semiconductor device structure also includes a first semiconductor element on the first fin structure and a second semiconductor element on the second fin structure. The first semiconductor element is wider than the second semiconductor element, and the first semiconductor element is closer to the substrate than the second semiconductor element.

公开(公告)号：US11710663B2

公开(公告)日：2023-07-25

申请号：US17194910

申请日：2021-03-08

申请人： Taiwan Semiconductor Manufacturing Company., Ltd.

发明人： Wen-Chun Keng ,  Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L21/311 ,  H01L21/3065

CPC分类号： H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0847

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first fin structure, a second fin structure, and a third fin structure over the semiconductor substrate. The semiconductor device structure also includes a merged semiconductor element on the first fin structure and the second fin structure and an isolated semiconductor element on the third fin structure. The semiconductor device structure further includes an isolation feature over the semiconductor substrate and partially or completely surrounding the first fin structure, the second fin structure, and the third fin structure. A top surface of the first fin structure is below a top surface of the isolation feature, and a top surface of the third fin structure is above the top surface of the isolation feature.

公开(公告)号：US08947900B2

公开(公告)日：2015-02-03

申请号：US14285362

申请日：2014-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Huai-Ying Huang ,  Yu-Kuan Lin ,  Sheng Chiang Hung ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Ping-Wei Wang

IPC分类号： G11C15/00 ,  G11C11/412 ,  G11C11/419

CPC分类号： G11C11/412 ,  G11C11/419

摘要： SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

摘要翻译： 描述SRAM单元和SRAM单元阵列。 在一个实施例中，SRAM单元包括与第一反相器交叉耦合的第一反相器和第二反相器，以形成第一数据存储节点和用于锁存值的互补的第二数据存储节点。 SRAM单元还包括第一栅极晶体管和开关晶体管。 第一栅极晶体管的第一源极/漏极耦合到第一数据存储节点，并且第一栅极晶体管的第二源极/漏极耦合到第一位线。 开关晶体管的第一源极/漏极耦合到第一通过栅极晶体管的栅极。

公开(公告)号：US12057505B2

公开(公告)日：2024-08-06

申请号：US17367497

申请日：2021-07-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/308 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/0228 ,  H01L21/3083 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4232 ,  H01L29/66545 ,  H01L29/6681

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first well region and a second well region and a first fin structure formed in a first region of the first well region. The semiconductor device structure also includes a second fin structure formed in a second region of the first well region. In addition, the second fin structure is narrower than the first fin structure. The semiconductor device structure also includes a third fin structure formed in a first region of the second well region. In addition, a sidewall of the first fin structure is substantially aligned with a sidewall of the third fin structure.

公开(公告)号：US12016169B2

公开(公告)日：2024-06-18

申请号：US17842208

申请日：2022-06-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ping-Wei Wang ,  Lien Jung Hung ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Yu-Kuan Lin ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Choh Fei Yeap

IPC分类号： H01L23/528 ,  G11C11/412 ,  G11C11/419 ,  H01L21/66 ,  H04N21/426 ,  H10B10/00 ,  H10B41/35

CPC分类号： H10B10/12 ,  G11C11/412 ,  G11C11/419 ,  H01L22/12 ,  H01L23/528 ,  H04N21/42692 ,  H10B10/00 ,  H10B41/35 ,  G11C2213/74 ,  G11C2213/79 ,  H01L2924/1437

摘要： A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.

公开(公告)号：US20230380128A1

公开(公告)日：2023-11-23

申请号：US18358573

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Ping-Wei Wang ,  Jui-Lin Chen ,  Yu-Kuan Lin

IPC分类号： H10B10/00 ,  G11C11/16 ,  G11C11/412 ,  H10B61/00 ,  H10N50/10

CPC分类号： H10B10/12 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1697 ,  G11C11/412 ,  H10B61/20 ,  H10N50/10

摘要： Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.

公开(公告)号：US11791214B2

公开(公告)日：2023-10-17

申请号：US17387636

申请日：2021-07-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Wei Lee ,  Chien-Yuan Chen ,  Jo-Chun Hung ,  Yung-Hsiang Chan ,  Yu-Kuan Lin ,  Lien Jung Hung

IPC分类号： H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/66742 ,  H01L29/7851 ,  H01L29/78696

摘要： A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

公开(公告)号：US20220367656A1

公开(公告)日：2022-11-17

申请号：US17387636

申请日：2021-07-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Wei Lee ,  Chien-Yuan Chen ,  Jo-Chun Hung ,  Yung-Hsiang Chan ,  Yu-Kuan Lin ,  Lien Jung Hung

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

摘要： A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.